Integrated PCS-FEC Architecture for Low-Latency Ethernet
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Solution Overview
Problem
Current Ethernet implementations experience significant latency due to the separation of Physical Coding Sublayer (PCS) and Forward Error Correction (FEC) functions, with redundant encoding and decoding processes contributing to increased latency, especially in high-speed applications like 100G Ethernet.
Innovation Solution
Integrating FEC functions within the PCS sublayer, eliminating redundant encoding/decoding steps and alignment markers, and performing FEC operations in the same clock domain as the PCS, thereby reducing latency by eliminating the need for data transmission to a separate FEC sublayer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC functions are implemented as a separate sublayer between PCS and PMA, then error correction capability is provided, but latency increases due to redundant encoding/decoding steps and data transmission between clock domains
Solution Approach 1:
The patent merges the FEC sublayer functions directly into the PCS sublayer, eliminating the separate FEC encoding and decoding stages. The PCS transmit structure performs both PCS encoding and FEC encoding in a single integrated process, while the PCS receive structure performs both PCS decoding and FEC decoding together. This integration removes redundant processing steps and eliminates the need for separate data transmission between PCS and FEC clock domains, thereby reducing latency while maintaining error correction capability.
2Stability of the object's composition
If data is transmitted between separate clock domains (first clock domain to second clock domain), then clock synchronization is achieved, but additional latency is introduced due to domain crossing requirements
Solution Approach 1:
The patent combines the FEC encoding and decoding operations within the same clock domain as the PCS operations. The FEC hardware modules are configured to operate in the first clock domain on the transmit side and in the second clock domain on the receive side, but the entire PCS+FEC processing chain is integrated such that data does not need to be transmitted between separate FEC and PCS clock domains. This eliminates domain crossing latency while maintaining proper clock synchronization through the integrated architecture.
3Manufacturing precision
If alignment markers are inserted and processed through separate FEC sublayer, then data alignment is achieved, but processing complexity and latency increase
Solution Approach 1:
The patent integrates alignment marker processing directly into the PCS sublayer operations, eliminating the need for separate alignment marker handling in a distinct FEC sublayer. The PCS transmit structure inserts alignment markers as part of the integrated PCS+FEC encoding process, and the PCS receive structure removes and processes them within the unified decoding architecture. This integration reduces processing complexity by eliminating redundant alignment operations while maintaining proper data alignment.
Data Source
AI summary
Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that inserts one or more alignment markers in the data and performs FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data, and remove the one or more alignment markers from the FEC decoded data.