Integrated PCS-FEC Architecture for Low-Latency Ethernet
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Solution Overview
Problem
Current Ethernet implementations experience significant latency due to redundant encoding and decoding processes and symmetrical functions between the Physical Coding Sublayer (PCS) and Forward Error Correction (FEC) sublayers, particularly in high-speed applications like 100G Ethernet.
Innovation Solution
Integrating FEC functions within the PCS sublayer, eliminating redundant encoding and decoding steps, and eliminating alignment markers on the transmit side, while performing similar optimizations on the receive side to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FEC sublayer is implemented as a separate layer between PCS and PMA sublayers following the classical Layered Functional Model, then the system follows standard Ethernet architecture and maintains layer independence, but the effective latency increases due to redundant encoding and decoding processes
Solution Approach 1:
The patent merges the FEC sublayer functions with the PCS sublayer by integrating the first FEC hardware module into the PCS transmit structure and the second FEC hardware module into the PCS receive structure. This consolidation eliminates the separate FEC sublayer, removing redundant encoding/decoding steps and reducing latency from over 500 ns to approximately 109 ns while maintaining all necessary error correction functions.
2Stability of the object's composition
If alignment markers are transmitted on the transmit side for synchronization, then clock domain synchronization is achieved, but the overall latency increases due to additional processing steps
Solution Approach 1:
The patent extracts and eliminates the alignment marker transmission function from the system. By removing this redundant synchronization mechanism and relying on the integrated FEC-PCS architecture's inherent timing relationships, the patent reduces latency while maintaining clock domain synchronization through the direct integration of hardware modules.
3Stability of the object's composition
If multiple separate hardware modules are used for FEC encoding and decoding in different clock domains, then clock domain isolation is maintained, but the device complexity and latency increase
Solution Approach 1:
The patent combines multiple separate hardware modules into integrated units by placing the first FEC hardware module within the PCS transmit structure and the second FEC hardware module within the PCS receive structure. This integration reduces device complexity and eliminates the need for separate FEC sublayer hardware while maintaining clock domain isolation through careful timing management within the unified architecture.
Data Source
AI summary
Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that performs FEC encoding, in a first clock domain, on the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data.