Integrated Photonic-Transistor Semiconductor Device
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Solution Overview
Problem
Current semiconductor devices require separate chips for photonics and transistors, leading to increased size and complexity, as well as higher manufacturing costs due to the need for independent fabrication processes for these components.
Innovation Solution
A semiconductor device is designed with a photonics device and a transistor integrated on the same chip, where the modulator and transistor are fabricated at the same vertical level, sharing common doped layers and insulating layers to simplify the manufacturing process and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If photonics device and transistor are integrated on the same chip, then device size is reduced and manufacturing is simplified, but fabrication process complexity increases due to requiring precise alignment and integration of different components at the same vertical level
Solution Approach 1:
The patent merges the photonics device and transistor fabrication processes into a single integrated flow. Both components are formed on the same chip substrate through shared manufacturing steps including doping, insulating layer deposition, and patterning, eliminating the need for separate chips and reducing overall device size while managing fabrication complexity through process integration
Solution Approach 2:
The patent employs universal manufacturing steps that serve multiple functions for both photonics and transistor components. The same doped layers, insulating layers, and fabrication processes are used to create both types of devices, allowing a single fabrication line to produce integrated photonic-transistor systems without requiring specialized separate processes
2Ease of manufacture
If separate chips are used for photonics device and transistor, then manufacturing fabrication is simpler for each component, but device size increases and additional packaging is required
Solution Approach 1:
The patent combines previously separate photonics and transistor chips into a single integrated device. By forming both components on the same substrate through integrated fabrication, the patent eliminates the need for additional packaging and inter-chip connections, reducing overall device size while maintaining manufacturability through standardized semiconductor processing
3Ease of manufacture
If modulator and transistor are fabricated at different vertical levels, then manufacturing is simpler, but device area increases and integration density decreases
Solution Approach 1:
The patent transitions from vertical stacking (different levels) to horizontal integration (same level) for the modulator and transistor. Both components are fabricated at the same vertical level on the chip substrate, allowing them to share the same fabrication processes and reducing the overall device area by eliminating the need for vertical separation and associated interconnect structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This integration miniaturizes the semiconductor device, simplifies the manufacturing process, and reduces costs by allowing both the photonics device and transistor to be fabricated using the same manufacturing steps, while maintaining the functionality of generating and driving optical signals.
Implementation Method 1
a photonics device disposed in the first region and configured to generate an optical signal
Implementation Method 2
a gate electrode spaced apart from the second doped layer in the first direction and disposed on the semiconductor layer
Data Source
AI summary
A semiconductor device includes a base substrate comprising a first region and a second region, a photonics device disposed in the first region, the photonics device comprising a first doped layer disposed on the base substrate, and a second doped layer disposed on the first doped layer so that at least a portion vertically overlaps the first doped layer, the second doped layer having a first vertical thickness, and a transistor disposed in the second region, the transistor comprising a semiconductor layer disposed on the base substrate and horizontally spaced apart from the first doped layer, and a gate electrode horizontally spaced apart from the second doped layer and disposed on the semiconductor layer, disposed at the same vertical level as that of the second doped layer, and having a second vertical thickness equal to the first vertical thickness.