Integrated Pixel and NVM Cell for In-Sensor Dot Product

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Solution Overview

Problem

Existing hardware-implemented neural network processors are discrete units, separated from pixel arrays, requiring data upload for cognitive computing, which hampers processing speed and efficiency in applications like image and voice processing.

Innovation Solution

An integrated pixel and two-terminal non-volatile memory (NVM) cell array within a processing chip, enabling deep in-sensor, in-memory computing by incorporating select transistors, NVM devices, and photodiodes, allowing for write, read, and functional computing modes, facilitating dot product computations without data upload.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If discrete processing units are used for hardware-implemented neural networks, then processing speed is improved, but data upload time and system complexity increase due to physical separation from pixel arrays

Engineering Contradiction:
Improveprocessing speedVSAvoiddata upload time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent merges the pixel array and processing unit into a single integrated sensor device. The pixel array captures images and the integrated processing unit performs neural network computations directly on the sensor chip, eliminating the need for separate data upload to discrete processors. This combination resolves the contradiction by maintaining fast processing while removing data transfer time.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The integrated sensor device performs multiple functions: image capture by the pixel array, data storage in memory cells, and neural network processing by the processing unit, all within a single device. This multi-functionality allows the system to process data immediately upon capture without requiring external processors, thus improving speed while eliminating data upload time.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If discrete processing units are used for neural network computations, then processing capability is improved, but device complexity and data transfer requirements increase

Engineering Contradiction:
Improvecomputational capabilityVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines the processing unit with the sensor device, integrating computational capability directly into the imaging system. This merger reduces system complexity by eliminating separate processing hardware while maintaining high computational capability for neural network operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a multi-device system (separate sensor and processor) to a single-integrated-device system. This dimensional change in system architecture consolidates multiple components into one unit, reducing overall system complexity while preserving computational capabilities through the integrated processing unit.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient dot product computations directly within the sensor, enhancing processing speed and reducing latency in neural network operations by integrating computing and memory functions within the same chip.

Implementation Method 1

The pixel can include a reset transistor, a photodiode connected in series with the reset transistor, and a sense node at a junction between the reset transistor and the photodiode

Methodology Applied
Scientific EffectPhotoelectric Effect: Photoelectric Effect

Data Source

PatentUS11195580B2Integrated pixel and two-terminal non-volatile memory cell and an array of cells for deep in-sensor, in-memory computing
Publication Date: 2021.12.07 GLOBALFOUNDRIES US INC
  • US11195580B2 patent drawing
  • US11195580B2 patent drawing
  • US11195580B2 patent drawing

AI summary

Disclosed is a cell that integrates a pixel and a two-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.