Integrated Post-Exposure Bake Track for Semiconductor Lithography
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Solution Overview
Problem
Current photolithographic cluster systems in semiconductor manufacturing face limitations in throughput due to stringent time variation requirements in process steps like post-exposure bake (PEB) and chill, which impact Critical Dimension Uniformity (CDU) and are constrained by the slowest wafer in a lot, leading to reduced overall cluster throughput.
Innovation Solution
A wafer processing system with a lithography tool, local track, transfer device handler, and interface unit, including a combined post-expose bake and chill unit, allows for tighter coupling of critical processes and independent scheduling, enabling better control over time-critical steps and increasing buffering on the output path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the track schedules around the slowest wafer to maintain process consistency, then Critical Dimension Uniformity (CDU) is improved, but the throughput of the entire track-lithography cluster is reduced
Solution Approach 1:
The patent segments the track into multiple independent processing lanes (first track, second track, third track) that can operate simultaneously. Each lane can process wafers independently, allowing fast wafers to proceed without being held back by slow wafers in other lanes, thereby maintaining high throughput while ensuring each lane maintains its own process consistency for CDU.
Solution Approach 2:
The patent introduces a temporal dimension to the scheduling by implementing a multi-lane architecture where wafers can be distributed across different tracks at different times. This allows the system to process multiple wafers in parallel with different timing characteristics, eliminating the bottleneck caused by sequential scheduling around the slowest wafer.
2Manufacturing precision
If the PEB step is tightly linked to the lithography step to control timing variation, then Critical Dimension Uniformity (CDU) is improved, but the flexibility in scheduling and overall throughput is reduced
Solution Approach 1:
The patent segments the PEB functionality into dedicated PEB chambers (first PEB chamber, second PEB chamber) that are integrated with specific lithography tools. This segmentation allows each lithography-PEB pair to maintain tight coupling for CDU control while the overall system gains flexibility through multiple independent processing paths.
Solution Approach 2:
The patent introduces intermediate buffer chambers and transfer mechanisms that act as mediators between lithography and PEB steps. These intermediaries allow for controlled timing variations while maintaining process consistency, providing both CDU control and scheduling flexibility simultaneously.
3Stability of the object's composition
If the track waits for slow lots to prevent stalling fast lots, then process stability is improved, but the throughput and efficiency of fast lots is reduced
Solution Approach 1:
The patent divides the single track into multiple parallel tracks (first track, second track, third track), each capable of independent operation. This allows fast lots to proceed through one track while slow lots are processed in another track, eliminating the stalling problem while maintaining process stability within each track through dedicated resource allocation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances CDU control, relaxes scheduling constraints, and increases throughput by locating critical processes closer together, allowing for separate coat and develop scenarios without impacting the lithography tool's performance.
Implementation Method 1
The PEB step is used to heat a substrate immediately after exposure to stimulate diffusion of the photoactive compounds and reduce the effects of standing waves in the photoresist layer
Implementation Method 2
The post-PEB chill step generally cools the substrate after the PEB step to a temperature at or near ambient temperature to assure that the substrate is at a defined temperature
Data Source
AI summary
Systems and methods for processing wafers, a combined post expose bake and chill unit, and an interface are disclosed. An exemplary system includes a lithography tool, local track, transfer device, transfer device handler, interface unit, and controller to schedule processing. An exemplary combined post expose bake and chill unit includes an enclosure having an opening in its side, and a bake unit and a chill unit in the enclosure. An exemplary interface includes a plurality of enclosures arranged around robot(s) that transfer wafers among the enclosures, one of the plurality of enclosures being an integrated bake and chill unit.