Integrated Power Package Thermal Management via Vertical Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated power packages face challenges in thermal and electrical performance due to the inability to place high-current transistors in a vertical stack and lack of exposed metal, which degrades thermal performance and electrical connectivity.
Innovation Solution
An integrated power package design featuring a substrate with an IC controller and transistors coupled to conductive support structures, allowing for efficient heat dissipation and improved electrical connectivity by exposing conductive elements for enhanced thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors are placed in a vertical stack with ICs, then device integration is improved, but thermal performance deteriorates
Solution Approach 1:
The patent transitions from planar lateral placement to vertical stacking architecture, utilizing the third dimension (height) to arrange transistors and ICs vertically. This dimensional change allows higher integration density while maintaining thermal performance through exposed metal surfaces that extend vertically for heat dissipation.
Solution Approach 2:
The package is segmented into distinct functional regions: an exposed metal region for thermal management, an insulator region for electrical isolation, and a substrate region for component mounting. This segmentation allows each region to optimize its specific function while working together as an integrated system.
2Temperature
If exposed metal is added to improve thermal performance, then thermal performance is improved, but device complexity increases
Solution Approach 1:
The exposed metal structures serve multiple functions simultaneously: they act as thermal pathways for heat dissipation, provide electrical interconnects between components, and serve as mechanical support structures. This multi-functionality reduces the need for separate dedicated thermal management components.
Solution Approach 2:
The patent merges thermal management functions with electrical interconnect functions by using the same exposed metal structures for both purposes. The metal traces and pads that provide electrical connectivity also serve as heat sinks and thermal conduction paths, eliminating the need for separate thermal management hardware.
3Ease of manufacture
If the same process step is used to interconnect controller and MOSFETs, then manufacturing is simplified, but electrical performance deteriorates
Solution Approach 1:
The interconnection process is segmented into multiple distinct steps: first forming the metal trace layer for low-current control signals, then adding a separate via layer for high-current power connections. This segmentation allows each interconnect type to be optimized for its specific electrical requirements rather than using a single compromise design.
Solution Approach 2:
Different regions of the package use different interconnection methods appropriate to their function: the insulator region uses precision via holes and metal traces for low-current control signals, while the exposed metal region uses direct bond wires or tab connections for high-current power paths. Each local region has interconnect quality matched to its electrical demands.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient heat transfer and improved electrical performance by placing transistors proximate to the IC controller, reducing package size and enhancing thermal performance through exposed conductive structures.
Implementation Method 1
exposed metal on top of the packages, which reduces the thermal performance of the MOSFETs and the controllers
Implementation Method 2
At least one electrical conductor is located between the first surface and another point on the substrate
Data Source
AI summary
An integrated power package includes a substrate having a first surface and an integrated circuit located within the substrate. At least one electrical conductor is located between the first surface and another point on the substrate. At least one transistor is electrically and mechanically coupled to the at least one first conductor. A support structure is electrically and mechanically coupled to the at least one transistor, wherein the at least one transistor is located between the first surface of the substrate and the support structure.