Integrated Power Structure Layout for 3D Semiconductor Contacts
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in integrating power structures within semiconductor devices, particularly in addressing the limitations of planar metal oxide semiconductor field effect transistors (FETs) and developing 3D structured FinFETs with improved electrical characteristics and processing efficiency.
Innovation Solution
A semiconductor device design featuring a substrate with active regions, device isolation layers, gate structures, source/drain regions, contact plugs, and integrated power structures that include a first power structure with varying widths and a second power structure penetrating the substrate, forming a unitary structure for enhanced electrical connectivity and processing facilitation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power structures are integrated within semiconductor devices to address high performance and high speed demands, then device functionality and performance are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The first power structure and second power structure are merged into a unitary integrated structure that penetrates through the substrate, combining multiple power delivery functions into a single cohesive component. This integration reduces the number of separate structures needed while maintaining enhanced electrical connectivity and performance.
Solution Approach 2:
The power structures extend in the third direction (vertical dimension) perpendicular to the substrate plane, transitioning from planar 2D layouts to 3D vertical architectures. This dimensional change enables improved power delivery through the substrate thickness while managing complexity through structured spatial arrangement.
2Reliability
If the first power structure has varying widths (first width at upper end, second width at lower end) to optimize electrical characteristics, then electrical performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The first power structure exhibits local quality variations with different widths at different locations - a first width at the upper end and a second width at the lower end. This localized dimensional variation optimizes electrical characteristics at different positions within the structure while maintaining overall manufacturability through controlled gradients.
3Reliability
If contact plugs are formed to extend into recesses in source/drain regions for electrical connection, then electrical connectivity is improved, but processing complexity increases
Solution Approach 1:
Recesses are formed in the source/drain regions before contact plugs are deposited, creating pre-prepared connection interfaces. This preliminary action of forming recesses ahead of time simplifies the subsequent contact plug formation process and ensures proper electrical connectivity without requiring complex post-processing steps.
Data Source
AI summary
A semiconductor device includes a substrate having an active region extending in a first direction, a gate structure on the active region, intersecting the active region and extending in a second direction, a source/drain region adjacent the gate structure and on the active region, a contact plug on the source/drain region and electrically connected to the source/drain regions, a first power structure on one side of the source/drain region in the second direction and electrically connected to the contact plug, and a second power structure penetrating the substrate and on a lower end of the first power structure. The first power structure and the second power structure are integrated as a unitary structure, and the first power structure has a first width at an upper thereof and a second width at the lower end thereof, the second width being equal to or greater than the first width.