Integrated Power Transistor Driver Circuit Segmentation

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Solution Overview

Problem

The integration of power transistors and driver circuits in a common semiconductor body poses a challenge due to high voltages applied during gate dielectric testing, which can damage the driver circuit if it lacks sufficient voltage blocking capability, leading to high on-resistance and driving losses.

Innovation Solution

The integration of a power transistor and a drive transistor with a drive circuit in a common semiconductor body, where the drive transistor has a relatively low voltage blocking capability, utilizing a half-bridge circuit with complementary transistors and a drift control region to reduce on-resistance and withstand testing voltages without damaging the driver circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the driver circuit transistor is designed with sufficiently high voltage blocking capability to withstand gate dielectric testing voltages, then the transistor can survive the testing process, but the on-resistance increases and driving losses increase

Engineering Contradiction:

Improvedriver circuit survival during testingVSAvoiddriving losses

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent divides the semiconductor body into distinct regions: a first region containing the power transistor and a second region containing the driver circuit transistor. This spatial segmentation allows each transistor to be optimized independently for its specific voltage requirements, enabling the driver transistor to have low voltage blocking capability (reducing on-resistance and driving losses) while the power transistor handles high voltages during testing.

Inventive Principle:

Principle #1Segmentation

2Loss of energy

If the driver circuit transistor is designed with low voltage blocking capability to reduce on-resistance and driving losses, then driving efficiency improves, but the transistor cannot withstand gate dielectric testing voltages

Engineering Contradiction:

Improvedriving lossesVSAvoiddriver circuit survival during testing

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If the power transistor and driver circuit are integrated in the same semiconductor body to save costs and space, then manufacturing efficiency and space utilization improve, but the driver circuit may be damaged by high testing voltages

Engineering Contradiction:

Improveintegration cost and spaceVSAvoiddriver circuit protection during testing

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

4Reliability

If the driver circuit transistor is designed with high voltage blocking capability to withstand testing voltages, then the transistor can survive gate dielectric testing, but the on-resistance increases leading to high driving losses

Engineering Contradiction:

Improvedriver circuit survival during testingVSAvoiddriving losses

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9893175B2Integrated circuit with a power transistor and a driver circuit integrated in a common semiconductor body

Publication Date: 2018.02.13 INFINEON TECH AUSTRIA AG

AI summary

An integrated circuit includes a power transistor and a drive circuit. The drive circuit includes at least one drive transistor. The power transistor and the at least one drive transistor are integrated in a common semiconductor body. The power transistor includes at least one transistor cell with a source region, a body region, a drift region, a drain region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. The at least one drive transistor includes active device regions integrated in a well-like structure comprising dielectric sidewall layers.