Integrated PSRO Clock Network for Accurate On-Chip Speed Screening
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Solution Overview
Problem
High-speed integrated circuit testing requires complex and expensive equipment, and existing performance-screen ring oscillators (PSROs) may not provide accurate data due to space constraints and placement issues, making it difficult to pinpoint performance issues.
Innovation Solution
A test signal distribution network with flushable pipeline latches that delivers test signals to local clock buffers across the integrated circuit, incorporating an input multiplexer and return path to form a PSRO, allowing for efficient and accurate characterization of device performance with minimal additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PSRO structures are placed on the integrated circuit to perform high-speed testing, then device performance can be measured, but the PSRO structures occupy large space on the integrated circuit
Solution Approach 1:
The patent merges the PSRO functionality with the existing test signal distribution network by integrating the oscillator signal path into the network's existing infrastructure. The test signal distribution network is configured to distribute both normal test signals and PSRO oscillator signals through shared pathways, reducing the additional space required for dedicated PSRO structures.
Solution Approach 2:
The test signal distribution network is designed to serve multiple functions: it distributes test signals for normal testing operations and simultaneously serves as the signal path for PSRO oscillation. This multi-functionality eliminates the need for separate dedicated PSRO signal paths, thereby reducing the overall space occupation on the integrated circuit.
2Measurement precision
If PSRO structures are placed at various points on the integrated circuit to measure performance, then device speed can be characterized, but the placement may not give accurate data as to the performance of the integrated circuit
Solution Approach 1:
The PSRO structures utilize the existing test signal distribution network infrastructure that is already present and optimized for signal distribution across the integrated circuit. By leveraging this established network, the PSRO measurement paths automatically benefit from the network's designed signal integrity features, routing optimization, and buffering capabilities, ensuring accurate performance data without requiring separate dedicated measurement paths.
3Productivity
If traditional PSRO structures are used for high-speed testing, then basic device speed can be screened, but complex and expensive equipment is required and it is difficult to pinpoint the root cause of issues
Solution Approach 1:
The integrated circuit performs self-testing through the PSRO implementation that utilizes its own internal test signal distribution network. The oscillator frequency is measured directly from the circuit's own signal paths without requiring external complex testing equipment. The circuit's existing infrastructure serves the dual purpose of normal operation and self-characterization, eliminating the need for expensive external high-speed testing equipment.
Data Source
AI summary
Embodiments relate to an integrated circuit comprising a performance-screen ring oscillator (PSRO). An aspect includes a test signal distribution network, the test signal distribution network including a plurality of flushable pipeline latches, the test signal distribution network configured to deliver a test signal simultaneously, via the plurality of flushable pipeline latches, to each of a plurality of local clock buffers associated with components of the integrated circuit at a plurality of signal outputs. Another aspect includes a PSRO including an input multiplexer that outputs an oscillator signal to an input of a branch of the test signal distribution network; and a return path from a signal output of the branch of the test signal distribution network to the input multiplexer.