Integrated Pull-Down FET for Power Unit Parasitic Inductance
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Solution Overview
Problem
In high-power switching applications, such as DC-DC converters, parasitic inductance in gate connections of power field effect transistors (FETs) leads to increased switching losses and potential circuit malfunctions like shoot-through and electromagnetic interference, due to longer turn-off times and voltage ringing.
Innovation Solution
Integrating pull-down FETs onto the same die as power FETs minimizes parasitic inductance from gate wires, reducing switching losses and increasing switching speed by providing a shorter electrical connection path for discharging during the turn-off cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If separate gate wire connections are used for power FETs, then device complexity is reduced and ease of manufacture is improved, but parasitic inductance increases leading to longer turn-off times and higher switching losses
Solution Approach 1:
The patent merges the pull-down FET and power FET onto the same IC die, creating an integrated structure where the gate connection path is minimized. This integration eliminates the need for separate gate wire connections, thereby reducing parasitic inductance and associated switching losses while maintaining manufacturing feasibility through standard semiconductor fabrication processes
2Productivity
If faster switching is implemented, then productivity is improved, but voltage ringing and shoot-through malfunctions increase due to parasitic inductance
Solution Approach 1:
By integrating the pull-down FET with the power FET on the same die, the patent creates an ultra-short gate connection path that minimizes parasitic inductance. This allows faster switching speeds to be achieved without the voltage ringing and shoot-through malfunctions that typically occur in conventional separate-connection architectures
Solution Approach 2:
The integrated pull-down FET is positioned to provide immediate counter-action during the turn-off cycle, rapidly discharging the gate capacitance before voltage ringing can occur. This preliminary anti-action prevents the harmful effects of parasitic inductance from manifesting as circuit malfunctions
3Ease of manufacture
If bond wire connections are used, then ease of manufacture is improved, but parasitic gate inductance increases leading to longer turn-off times
Solution Approach 1:
The patent integrates the pull-down FET and power FET in the same semiconductor die, eliminating the need for bond wire connections between separate components. This integration reduces the gate connection path to minimal trace lengths within the die, dramatically reducing parasitic inductance and turn-off time while maintaining ease of manufacture through standard semiconductor fabrication
Solution Approach 2:
The patent extracts the gate connection path from the external bond wire domain and relocates it to the internal die domain, where connection lengths are minimized. This extraction eliminates the dominant source of parasitic inductance while keeping the manufacturing process simple and scalable
Data Source
AI summary
One example relates to a circuit that includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die has a power field effect transistor (FET) and a pull-down FET coupled to the power FET. The second integrated circuit die has a pull-up FET coupled to the power FET.