Integrated Ramp Signal Circuit for Linear Display Driving
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current System on Glass (SOG) technology struggles to effectively integrate a ramp signal generator, leading to increased area requirements and poor linearity in display panels, hindering miniaturization and display quality.
Innovation Solution
A ramp signal generating circuit comprising a first shift register, a second shift register, and a voltage decreasing unit, with a sampling unit, that sequentially and evenly decreases power supply voltages, allowing for high integration and improved linearity through controlled voltage output and sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a ramp signal generator is additionally arranged in the array substrate, then the display panel can drive various models requiring ramp signals, but the area of the driving circuits is increased greatly
Solution Approach 1:
The patent combines the ramp signal generator with the existing dual shift register structure already present in the array substrate. The voltage decreasing unit shares the same physical space and timing control resources as the shift registers, merging multiple functions into a unified circuit architecture. This eliminates the need for a separate dedicated ramp signal generator while maintaining the capability to drive various display models requiring ramp signals.
Solution Approach 2:
The voltage decreasing unit is designed to serve multiple purposes: it generates ramp signals for DA converters, provides timing control for sampling operations, and integrates with the existing shift register timing system. By making the voltage decreasing unit multi-functional, the circuit achieves adaptability to drive various display models without requiring additional dedicated circuits for each function.
2Extent of automation
If current SOG technology is used to integrate a ramp signal generator, then system integration is achieved, but the linearity of the generated ramp signal is poor
Solution Approach 1:
The voltage decreasing unit is divided into multiple stages with n voltage decreasing resistors and n first transistors arranged alternately in columns. Each stage contributes to the overall voltage decrease in a controlled manner, with the first shift register controlling each transistor row sequentially. This segmentation allows for precise control of the voltage decrease process, improving linearity while maintaining integration.
Solution Approach 2:
The patent implements a feedback mechanism where the second shift register controls the sampling unit to sample and output the voltages decreased by the voltage decreasing unit. This sampling and output control creates a feedback loop that ensures the ramp signal generation process maintains accuracy and linearity, allowing the integrated circuit to achieve good signal quality despite the constraints of SOG technology.
3Manufacturing precision
If more voltage stages are achieved with higher sampling frequency, then linearity of ramp signal is improved, but the circuit complexity increases
Solution Approach 1:
The first shift register is configured to control the voltage decreasing unit to output voltages which are decreased continuously stage by stage before the sampling operation. This preliminary action of sequentially controlling each transistor row ensures that the voltage decreases in a predetermined, linear fashion before the second shift register performs the sampling. By preparing the voltage sequence in advance, the circuit achieves high linearity without requiring complex real-time control mechanisms during sampling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the area occupied by the ramp signal generating circuit, enhances linearity, and supports higher sampling frequencies, enabling more voltage stages and smaller voltage steps, thus improving the quality of the ramp signal.
Implementation Method 1
the voltage decreasing unit comprises 2n rows in which n rows are resistor rows and the other n rows are transistor rows; in each of the resistor rows, only n voltage decreasing resistors are arranged
Implementation Method 2
the voltage decreasing unit is configured to sequentially and evenly decrease a first power supply voltage inputted from the first power supply input terminal and a second power supply voltage inputted from the second power supply input terminal respectively
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first shift register (11), a second shift register (12), a voltage decreasing unit (13) and a sampling unit (14); the voltage decreasing unit (13) is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register (11) is connected to the voltage decreasing unit (13) and is configured to control the voltage decreasing unit (13) to output voltages which are decreased continuously stage by stage; the sampling unit (14) has an output terminal and is connected to the voltage decreasing unit (13); the second shift register (12) is connected to the sampling unit (14) and is configured to control the sampling unit (14) to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit (13). Such ramp signal generating circuit is capable of reducing area of the ramp signal generating circuit and improving linearity of ramp signal.