Integrated Resistor Network Layout for High Voltage Resolution
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Solution Overview
Problem
Conventional resistor networks in integrated circuits face challenges in scaling resistance values without increasing surface area or parasitic capacitance, which affects voltage resolution and performance.
Innovation Solution
A resistor network architecture with a first number of integrated resistors in series, a second number in parallel, and a third number in series between the second resistors, maintaining equal resistance values and dimensions to achieve reduced area and improved voltage resolution, specifically using a 2n resistor configuration that reduces the number of resistors and surface area while maintaining equivalent voltage resolution to a conventional n2 resistor network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of resistors in a conventional n2 array is increased to improve voltage resolution, then voltage resolution is improved, but surface area increases by a factor of n2
Solution Approach 1:
The patent divides the resistor network into three distinct groups: a first group of n resistors in series, a second group of n-1 resistors in parallel, and a third group of 1 resistor in series. This segmentation allows the network to achieve n-level voltage resolution while using only 2n resistors total, compared to the conventional n2 array requirement, thereby reducing surface area by a factor of n/2.
2Area of stationary object
If the number of resistors is reduced to decrease surface area, then surface area is reduced, but voltage resolution deteriorates
Solution Approach 1:
The patent changes the architectural parameters of the resistor network from a two-dimensional n×n array to a specific series-parallel configuration with groups of n, n-1, and 1 resistors. This parameter change maintains the voltage division ratio of 1/n across the first group while reducing the total resistor count from n2 to 2n, achieving both area reduction and preserved voltage resolution.
3Area of stationary object
If individual resistor dimensions are scaled down to reduce area, then area is reduced, but resistance values do not scale proportionally due to fabrication variations
Solution Approach 1:
The patent ensures that all resistors in the network, regardless of their position in different groups, have identical physical dimensions (length L and width W) and are fabricated using the same process parameters. This local uniformity in resistor quality compensates for the reduced total area, as fabrication variations affect all resistors equally, maintaining consistent resistance ratios and accurate voltage division.
Data Source
AI summary
A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n−1, and the third number is 1, the total number of resistors is 2n.