Integrated Scan Driver Circuit for Display Dead Space Reduction

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Solution Overview

Problem

Existing display devices have dead space issues due to the separate placement of scan drivers and power lines, which can lead to inefficiencies and potential image flicker, especially in low-frequency driving.

Innovation Solution

The display device integrates some scan drivers and electrically and physically separates the power lines connected to different drivers, allowing for independent voltage supply to each driver and reducing the dead space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If scan drivers are placed separately with dedicated power lines, then each driver receives stable voltage supply, but dead space increases and image flicker occurs in low-frequency driving

Engineering Contradiction:
Improvevoltage supply stabilityVSAvoiddead space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple scan drivers (first scan driver and second scan driver) into a single integrated scan driver structure. This integration reduces the dead space that would otherwise be required for separate driver placements, while maintaining the functional separation through internal circuit design that prevents voltage interference.

Inventive Principle:
Principle #5Merging (Combining)

2Area of stationary object

If power lines are shared among multiple drivers, then dead space is reduced, but voltage supply stability deteriorates and image flicker increases

Engineering Contradiction:
Improvedead spaceVSAvoidvoltage supply stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent segments the power supply function by providing dedicated power lines from separate power pads to different scan drivers, even though the drivers are physically integrated. This segmentation ensures that voltage fluctuations in one driver do not affect others, maintaining supply stability while achieving space efficiency through integration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces power pads as intermediary connection points between the power supply and scan drivers. These pads serve as dedicated interface points that isolate the power distribution paths, preventing electrical interference between drivers while allowing compact integration of the driver circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If scan drivers are integrated, then dead space is reduced and efficiency improves, but circuit complexity increases

Engineering Contradiction:
Improvedead spaceVSAvoidcircuit complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The integrated scan driver is designed with multi-functional capability, where a single driver structure can selectively operate in different modes (first scan driver mode, second scan driver mode, or both simultaneously) based on external control signals. This universality reduces the need for completely separate driver circuits while maintaining the functional flexibility required for different display configurations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250046256A1Display device
Publication Date: 2025.02.06 SAMSUNG DISPLAY CO LTD
  • US20250046256A1 patent drawing
  • US20250046256A1 patent drawing
  • US20250046256A1 patent drawing

AI summary

A gate driver including a plurality of stages, each of the plurality of stages including an eighth transistor connected between a third power input terminal and an output terminal, the eighth transistor including a gate electrode connected to a fourth node, a seventh transistor connected between a second power input terminal and the output terminal, the seventh transistor including a gate electrode connected to a third node, an eleventh transistor connected between the third power input terminal and the fourth node, the eleventh transistor including a gate electrode connected to a first node, a twelfth transistor connected between the first node and the third node, the twelfth transistor including a gate electrode connected to the second power input terminal, and a third capacitor connected between the third power input terminal and the fourth node.