Integrated Security Device Logic Circuit Glitch Detection
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Solution Overview
Problem
Existing security protocols require separate circuits for PUF, physical random number generation, and encryption, leading to a large circuit scale and the need for individual testing.
Innovation Solution
An integrated security device and signal processing method that combines these functions using a logic circuit with a selector and glitch detector to generate a physical random number and device identifier, reducing circuit scale and facilitating testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuits are used for PUF, physical random number generation, and encryption functions, then each function can be independently implemented and tested, but the overall circuit scale becomes large and testing complexity increases
Solution Approach 1:
The patent merges three separate security functions (PUF, physical random number generation, and encryption) into a single integrated circuit. The encryption circuit is configured to operate in multiple modes: as a PUF by detecting glitches at intermediate nodes, as a physical random number generator by selecting and processing glitch signals, and as an encryption device for secure communication. This consolidation reduces the overall circuit scale while maintaining functional independence through mode switching.
Solution Approach 2:
The encryption circuit is designed with multi-functionality to perform diverse security operations. By incorporating a selector that can choose different intermediate node signals and configuring the circuit to respond to control signals, the same hardware infrastructure executes PUF authentication, random number generation, and encryption tasks, eliminating the need for separate dedicated circuits for each function.
2Reliability
If separate circuits are used for PUF, physical random number generation, and encryption, then each circuit can be optimized for its specific function, but the number of tests required increases
Solution Approach 1:
The patent consolidates three security functions into one circuit, which directly reduces the number of separate tests required. Instead of independently testing PUF circuits, random number generation circuits, and encryption circuits, the integrated design allows a single comprehensive test to validate all functions through mode switching, significantly improving testing efficiency.
3Device complexity
If a single integrated circuit is used for PUF, random number generation, and encryption, then circuit scale is reduced, but the circuit must perform multiple functions which increases design complexity
Solution Approach 1:
The encryption circuit is designed with universal capabilities to perform PUF authentication, random number generation, and encryption. The selector chooses different intermediate node signals based on the required function, and the circuit responds to control signals to execute the appropriate operation mode, enabling one circuit to fulfill multiple security roles without requiring separate dedicated hardware for each function.
Solution Approach 2:
The circuit employs dynamic mode switching to adapt its functionality. Control signals direct the circuit to operate in different modes (PUF, random number generation, or encryption) as needed, allowing the same hardware to dynamically reconfigure its behavior based on operational requirements, thereby achieving functional versatility without increasing physical circuit scale.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated approach allows for a single circuit to perform PUF, random number generation, and encryption functions, reducing circuit complexity and simplifying testing processes.
Implementation Method 1
a signal processing unit having a function of detecting a glitch caused by the signals corresponding to the specific number of lines selected by the selector
Data Source
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AI summary
Provided is an integrated security device, including: an encryption/decoding processing unit (11) for executing processing necessary for authentication by using a logic circuit that forms an encryption/decoding function; a selector (12) for selecting signals whose number corresponds to a specific number of lines from among signals from a plurality of intermediate nodes of the logic circuit in accordance with a selection signal; and a signal processing unit (13) having a function of detecting a glitch caused by the signals corresponding to the specific number of lines, for implementing both a function of generating a physical random number and a function of generating a device identifier by a physical characteristic based on the glitch detected by switch-selecting the signals corresponding to the specific number of lines.