Integrated Semiconductor Packaging for Half-Bridge Switching Loss Reduction
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Solution Overview
Problem
Existing semiconductor power supply systems face challenges in minimizing switching loss and parasitic effects due to parasitic inductance and impedance, which affect the safety and efficiency of power conversion in half-bridge circuits.
Innovation Solution
A semiconductor packaging structure that integrates upper and lower tubes of the bridge arm switch inside the chip, eliminating the need for external connections and minimizing the size of these components, thereby reducing the impact of parasitic inductance and resistance, and allows the power electrode and ground terminal to be routed from the same side for easier capacitor placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If switching speed is increased to decrease switching loss, then switching loss is reduced, but peak voltage increases due to parasitic inductance threatening element safety
Solution Approach 1:
The patent merges the upper and lower tube components into a single integrated chip structure. This integration minimizes the loop area between the bridge arm switch and decoupling capacitor, thereby reducing parasitic inductance. The reduced parasitic inductance allows for faster switching speeds without generating excessive peak voltages, thus decreasing switching loss while maintaining element safety.
Solution Approach 2:
The patent routes the power electrode and ground terminal from the same side of the chip, creating a planar layout that minimizes the current loop area. This dimensional arrangement reduces the parasitic inductance in the switching path, enabling faster switching without compromising element safety from voltage spikes.
2Ease of manufacture
If upper and lower tubes are connected externally, then circuit functionality is achieved, but parasitic inductance and resistance increase affecting system efficiency
Solution Approach 1:
The patent combines both upper and lower tubes within a single chip, eliminating the need for external connections between these components. This integration removes the parasitic inductance and resistance associated with external wiring, thereby improving system efficiency while maintaining ease of manufacture through a monolithic structure.
3Loss of energy
If elements are integrated inside the chip, then parasitic inductance and resistance are reduced, but device complexity increases
Solution Approach 1:
The patent integrates multiple power semiconductor devices (upper and lower tubes) into a single chip with a unified structure. This merging approach reduces parasitic inductance and resistance by minimizing internal connections, while the standardized integration methodology keeps the manufacturing process manageable despite the increased functional density.
Data Source
AI summary
A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.