Integrated Shift Register for Narrow-Bezel OLED Driving
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Solution Overview
Problem
The existing circuit design for OLED display devices is complex and occupies large space due to separate gate driving and light emitting driving circuits, which hinders the implementation of narrow bezel designs.
Innovation Solution
A shift register with integrated control and output circuits that simultaneously provide gate driving and light emitting control signals, reducing circuit complexity and space by using a single integrated circuit for both functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate driving circuit and light emitting driving circuit are separately disposed, then each circuit can be independently designed and controlled, but the circuit design becomes complicated and the occupied space increases
Solution Approach 1:
The patent combines the gate driving circuit and light emitting driving circuit into a single integrated shift register unit. The shift register simultaneously generates both gate driving signals (from first output terminal) and light emitting control signals (from second output terminal), eliminating the need for separate discrete circuits and reducing overall design complexity
Solution Approach 2:
The shift register is designed with multi-functional capability to serve dual purposes: it acts as both a gate driving circuit and a light emitting driving circuit. By using the same shift register structure to generate different types of control signals through different output terminals, the patent achieves circuit simplification while maintaining independent control functionality
2Reliability
If gate driving circuit and light emitting driving circuit are separately disposed, then each circuit can be independently designed and controlled, but the occupied space becomes large
Solution Approach 1:
The patent merges two previously separate driving circuits into one integrated shift register, directly reducing the total occupied space. The unified structure shares common components such as the shift register stages, clock signal inputs, and power supply connections, eliminating redundant circuit elements and minimizing the area required in the non-display region
3Adaptability or versatility
If separate gate driving and light emitting driving circuits are used, then circuit functionality is complete, but the design is not favorable for narrow bezel implementation
Solution Approach 1:
The integrated shift register design reduces the area occupied in the non-display region, creating more space available for narrowing the bezel. By consolidating the driving circuits, the patent minimizes the footprint in the peripheral area while preserving all necessary circuit functionalities
4Device complexity
If integrated shift register is used to provide both gate driving and light emitting control signals, then circuit design is simplified and space is reduced, but circuit functionality must be multi-functional
Solution Approach 1:
The shift register is designed with inherent multi-functionality to simultaneously provide gate driving signals and light emitting control signals. By incorporating multiple output terminals (first output terminal for gate signals, second output terminal for light emitting signals) within the same shift register structure, the patent achieves circuit simplification without sacrificing the required functional versatility
Data Source
AI summary
A shift register includes: a first control and output circuit coupled to precharge signal input terminal, first and second power supply terminals, first to third clock signal terminals, first signal output terminal, and configured to write second clock signal provided through the second clock signal terminal to the first signal output terminal during precharge and output phases, and write second operating voltage provided through the second power supply terminal to the first signal output terminal during reset phase; and a second control and output circuit coupled to the first and second power supply terminals, the third clock signal terminal, the precharge signal input terminal, second signal output terminal, and configured to write first operating voltage provided through the first power supply terminal to the second signal output terminal during the precharge and output phases, and write the second operating voltage to the second signal output terminal in the reset phase.