Integrated Source-Drain Silicidation and Dopant Activation

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Solution Overview

Problem

The high manufacturing cost and thermal budget associated with the formation of transistors in integrated circuits, due to multiple process steps and thermal processes involved in forming gate dielectrics, gate electrodes, source and drain regions, and silicide regions, necessitate a more efficient approach.

Innovation Solution

A method involving the formation of a gate stack over a semiconductor region, deposition of an impurity layer, and a metal layer, followed by an annealing process where the impurity elements are diffused into the semiconductor region to form source/drain regions and silicide regions, sharing a reduced thermal budget by combining activation and silicidation processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate thermal processes are used for activation and silicidation, then each process can be optimized independently, but the total thermal budget increases and manufacturing cost increases

Engineering Contradiction:

Improveprocess optimizationVSAvoidthermal budget

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent combines the activation process and silicidation process into a single thermal annealing step. The metal layer is deposited over the doped semiconductor region, and both activation of dopants and formation of silicide occur simultaneously during one thermal treatment, eliminating the need for separate thermal processes and reducing total thermal budget.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The metal layer serves multiple functions: it acts as a cap layer during doping, provides the metal source for silicide formation, and enables both activation and silicidation to occur during the same thermal process. This multi-functionality allows one thermal step to achieve what traditionally required two separate steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple process steps are used for transistor formation, then each component can be formed with proper control, but manufacturing cost increases

Engineering Contradiction:

Improvecomponent controlVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges the formation of source/drain regions and silicide regions into a single process sequence. Dopant implantation is followed by metal layer deposition and a single annealing step that simultaneously activates dopants and forms silicide, reducing the total number of process steps while maintaining control over each component's formation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The metal layer is deposited in advance, before the annealing step, so that it is already in position to serve as both cap layer and silicide source. This preliminary action enables the metal layer to protect the doped region during implantation and then participate in silicide formation during the subsequent annealing.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If traditional separate processes are used for activation and silicidation, then impurity activation can be achieved, but impurity loss occurs and thermal expenditure increases

Engineering Contradiction:

Improveimpurity activationVSAvoidimpurity loss

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The metal layer is deposited as a cap layer before the annealing process, creating a protective barrier over the doped semiconductor region. This cap layer prevents impurity loss during thermal processing by containing the dopants within the semiconductor region while still allowing them to be activated, thus cushioning against the harmful effect of impurity loss.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces the thermal budget and manufacturing costs by enabling the activation of source and drain regions with a metal layer acting as a cap, preventing impurity loss and sharing the annealing process for silicidation and activation, resulting in efficient impurity concentration and reduced thermal expenditure.

Implementation Method 1

the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region

Methodology Applied

Scientific EffectDiffusion: Diffusion

Implementation Method 2

An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing

Methodology Applied

Scientific EffectAnnealing: Annealing

Implementation Method 3

the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region

Methodology Applied

Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS10157995B2Integrating junction formation of transistors with contact formation

Publication Date: 2018.12.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.