Integrated Simulator and Analysis Engine for Semiconductor Power Optimization
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Solution Overview
Problem
Current semiconductor design processes are computationally intensive due to the need for full-scale simulation of billions of logic components, leading to significant time consumption and inefficiency in reducing dynamic power consumption, particularly in addressing glitch power, which accumulates inaccuracy over iterative optimization steps.
Innovation Solution
An integrated simulator and analysis and optimization engine system that performs both full-scale and incremental simulations, allowing for communication and interaction through APIs, enabling localized and incremental power analysis and optimization, reducing the computational burden by focusing on specific areas and time periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-scale simulation is performed on billions of logic components, then accurate power analysis is achieved, but computational time and resource consumption increase significantly
Solution Approach 1:
The patent divides the full-scale circuit simulation into multiple incremental simulation steps, where each step simulates a portion of the circuit or a specific time window. This segmentation allows the optimizer to focus on localized changes without re-simulating the entire circuit, thereby maintaining accuracy while reducing computational time significantly.
Solution Approach 2:
The patent performs preliminary full-scale simulation once to establish baseline power consumption data and identify critical circuit regions. Subsequent optimizations use this pre-established information to guide incremental simulations, avoiding the need to repeatedly simulate the entire circuit and thus reducing total simulation time while maintaining accuracy.
2Loss of energy
If iterative optimization is performed with repeated full-scale simulations, then power consumption is reduced, but the optimization process becomes computationally intensive and time-consuming
Solution Approach 1:
The patent implements a dynamic simulation strategy where the simulation scope and depth adapt based on the optimization stage. Early iterations use coarser-grained incremental simulations for quick feedback, while later iterations focus on refined local simulations around identified hotspots. This dynamic approach accelerates the optimization process while maintaining power reduction effectiveness.
Solution Approach 2:
The patent establishes a feedback loop where incremental simulation results are immediately fed back to the optimizer to guide the next optimization step. This continuous feedback mechanism enables the system to converge faster on optimal solutions by learning from each incremental simulation result, reducing the total number of iterations needed and thus improving optimization speed.
3Loss of time
If incremental simulation is used to reduce computational burden, then simulation time is reduced, but maintaining accuracy across iterative optimization steps becomes challenging
Solution Approach 1:
The patent implements a nested simulation structure where incremental simulations are embedded within the broader optimization framework. Each incremental simulation focuses on a specific subset of the circuit or time window, nested within the overall design space. This nesting allows detailed local analysis without sacrificing global context, maintaining accuracy while reducing computational burden.
Solution Approach 2:
The patent introduces an intermediary layer that bridges incremental simulations with full-scale accuracy requirements. This intermediary performs selective aggregation of incremental results and applies correction factors based on pre-computed full-scale baseline data, ensuring that localized incremental analyses maintain global accuracy without requiring repeated full-scale simulations.
Data Source
AI summary
A signoff process includes: accessing circuit information of a circuit; performing, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern; performing, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the input pattern used in the power analysis and optimization; and outputting a simulation result to the analysis and optimization engine; wherein the analysis and optimization engine and the simulator are integrated.