Integrated SRAM ROM Memory Cell for Miniaturization
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Solution Overview
Problem
The existing semiconductor memory technologies, such as ROMs and SRAMs, occupy a large amount of space due to their separate implementations, making it difficult to miniaturize data processing devices while maintaining their functional capabilities.
Innovation Solution
A memory cell combining a Static Random Access Memory (SRAM) cell with a Read Only Memory (ROM) cell, where the ROM cell sets the logic states of internal latch nodes of the SRAM cell when triggered, allowing for a single memory solution that operates in both SRAM and ROM modes, reducing overall device size and sharing peripheral circuitries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ROM and SRAM are implemented separately, then their functional capabilities are maintained, but the device size becomes large
Solution Approach 1:
The patent combines ROM and SRAM into a single memory cell structure by integrating a ROM cell with a SRAM cell. The ROM cell includes a first transistor connected to ground, while the SRAM cell includes a basic RS flip-flop with two internal latch nodes. This merging allows both memory types to coexist in one cell, reducing overall device area while maintaining both functional capabilities.
Solution Approach 2:
The combined memory cell achieves multi-functionality by enabling the same physical structure to operate as either ROM or SRAM depending on the triggering signal. When the triggering signal is activated, the ROM cell sets the logic states of the SRAM cell's latch nodes, allowing the cell to function as ROM. When the triggering signal is inactive, the cell operates as SRAM, providing universal functionality from a single structure.
2Adaptability or versatility
If ROM cell structure is added to SRAM cell, then ROM functionality is achieved, but the cell size increases
Solution Approach 1:
The invention merges the ROM cell structure with the SRAM cell structure into a single integrated cell. The ROM cell comprises a first transistor whose drain is connected to ground and whose gate receives a triggering signal. The SRAM cell comprises a basic RS flip-flop with internal latch nodes. By merging these structures, the patent achieves ROM functionality without proportionally increasing cell size, as both functions share the same physical space.
Solution Approach 2:
The integrated memory cell achieves universality by enabling it to function as either ROM or SRAM based on the triggering signal state. This multi-functionality allows the cell to provide ROM capabilities (data preservation after power down) and SRAM capabilities (high-speed access and reprogrammability) without requiring separate dedicated structures for each function, thereby optimizing cell size.
3Reliability
If separate ROM and SRAM cells are used, then specific functions are maintained, but peripheral circuitries cannot be shared
Solution Approach 1:
The patent merges ROM and SRAM into a single memory cell structure, which enables sharing of peripheral circuitries such as bit lines, word lines, and decoding circuits. The combined cell structure allows both memory types to access common peripheral resources, reducing the overall number of peripheral circuitries needed while maintaining the reliability and specific functions of both ROM and SRAM operations.
Data Source
AI summary
In various embodiments, a memory cell and a memory are provided. The memory cell comprises a Static Random Access Memory (SRAM) cell including a reset-set (RS) flip-flop and a Read Only Memory (ROM) cell being connected (or coupled) to the SRAM cell to set logic states of internal latch nodes of the RS flip-flop when the ROM cell is triggered. The size of the memory cells proposed in an embodiment of the invention is much smaller than the sum of the size of ROM cells and the size of SRAM cells with the capacity of the memory cells same as the sum of the capacity of the ROM cells and the capacity of the SRAM cells.