Integrated Standard Cell Structure: Uniform Gates for Dense Abutment
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Solution Overview
Problem
The existing design of integrated circuits (ICs) using standard cells results in increased area requirements due to reserved spaces between cells, complicating fabrication and degrading circuit performance, yield, and design efficiency.
Innovation Solution
The IC layout incorporates standard cells with predefined rules, utilizing uniform gate stacks in transition areas and dummy gates for abutment, reducing the need for complex lithography processes and minimizing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard cells are placed with reserved spaces according to pre-defined rules, then fabrication complexity and defect risk are reduced, but the circuit area increases significantly
Solution Approach 1:
The patent extracts the transition area structures (dummy gates, uniform gate stacks) from the standard cell design and relocates them to the inter-cell transition regions. This allows the reserved spaces to be minimized while the extracted structures handle the fabrication uniformity requirements, thus reducing overall circuit area without compromising manufacturability
Solution Approach 2:
The patent introduces transition areas as intermediary regions between adjacent standard cells. These transition areas contain dummy gates and uniform gate stacks that act as mediators to maintain fabrication uniformity across cell boundaries, enabling tighter cell spacing while preserving manufacturing ease
2Ease of manufacture
If reserved spaces are increased between standard cells, then fabrication difficulty and defect risk are reduced, but circuit performance is degraded
Solution Approach 1:
The patent extracts the performance-degrading structures from within the standard cells and places them in transition areas. This allows standard cells to be placed closer together without the performance penalty of internal dummy structures, maintaining circuit performance while preserving fabrication simplicity through the extracted transition area designs
3Area of stationary object
If standard cells are placed closer together to reduce area, then circuit area is reduced, but fabrication complexity and defect risk increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring transition areas with dummy gates and uniform gate stacks before placing standard cells. This preliminary preparation ensures that when cells are placed closer together, the pre-established transition structures automatically maintain fabrication uniformity, enabling dense packing without increasing fabrication complexity
Solution Approach 2:
The transition areas serve as intermediary buffers between closely-spaced standard cells. These intermediaries contain the necessary dummy structures and uniform gate stacks that resolve the fabrication uniformity issues that would otherwise arise from tight cell spacing, thus enabling area reduction without compromising manufacturability
4Ease of manufacture
If reserved spaces with structures are increased, then fabrication difficulty is reduced, but yield decreases due to increased defects
Solution Approach 1:
The patent extracts all necessary fabrication-assist structures (dummy gates, uniform gate stacks) from within standard cells and concentrates them in transition areas. This extraction eliminates internal defect sources within cells while concentrating potential issues in dedicated transition regions, thereby reducing overall defect rates while maintaining fabrication simplicity
Solution Approach 2:
The transition areas act as intermediary zones that isolate fabrication complexity from the standard cells themselves. By placing dummy structures and uniform gate stacks in these intermediaries, the patent protects the main cell structures from fabrication defects, thus reducing yield-impactful defects while preserving ease of manufacture
Data Source
AI summary
An IC includes a first standard cell (SC1) having a first circuit area (CA1) and a first transition area (TA1) placed on an edge of the CA1; and a SC2 having a CA2 and a TA2 placed on an edge of CA2′. CA1 includes a first and a second active region (AR1 and AR2) longitudinally oriented along a first direction (D1), and a first gate stack (G1) along a D2-D1 and extending over AR1 and AR2. G1 includes a first gate segment (GS1) contacting AR1 and a GS2 contacting AR2. GS1 and GS2 are different in composition. GS1 and GS2 are associated with a pFET and a nFET, respectively. TA1 includes a G2 longitudinally oriented along D2 and spans between opposite cell edges of the SC1. G2 is a lengthwise uniform gate stack. SC2 is placed in abutment with the SC1 such that TA1 and TA2 share a common edge.