Integrated Static Memory Cell with Vertical Transistor Stacking
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Solution Overview
Problem
Current static memory cell designs are less dense compared to dynamic memory cells, which limits their integration in highly compact applications due to the need for multiple transistors and lack of internal feedback for maintaining stable output voltages.
Innovation Solution
The design incorporates six transistors configured as adjacent disks, with p-channel and n-channel transistors forming inverters and flip-flops, utilizing conductive pillars and interconnects to maintain stable operating states, suitable for highly integrated assemblies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static memory cells use multiple transistors to maintain stable operating states, then reliability is improved, but device area increases reducing density
Solution Approach 1:
The patent merges the pull-up transistor and pull-down transistor into a single integrated structure where the source/drain regions of the pull-up transistor are formed over and merged with the source/drain regions of the pull-down transistor. This integration reduces the total area occupied by the memory cell while maintaining the necessary transistor functions for stable operation.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical structure by stacking the pull-up transistor above the pull-down transistor. This vertical integration allows multiple transistor functions to be packed into a smaller footprint area, improving density while preserving reliability.
2Area of stationary object
If dynamic memory cells use single transistor design, then area is reduced improving density, but stability of output voltage deteriorates requiring periodic refreshing
Solution Approach 1:
The patent implements cross-coupled feedback between the pull-up and pull-down transistors through shared source/drain regions and gate connections. This feedback mechanism creates bistable operation where the output voltage is automatically maintained at stable high or low levels without requiring periodic refreshing, eliminating the instability problem of dynamic memory cells.
Solution Approach 2:
The memory cell structure is designed to self-maintain its output voltage through internal feedback mechanisms. The cross-coupled transistor arrangement automatically reinforces the current state, making the cell self-sustaining without external intervention or periodic refreshing operations.
3Ease of manufacture
If static memory cells are designed with traditional architectures, then ease of manufacture is maintained, but integration density decreases limiting compact applications
Solution Approach 1:
The patent segments the memory cell into distinct functional layers: the pull-down transistor layer, the shared source/drain region layer, and the pull-up transistor layer. This segmentation allows each component to be manufactured using standard CMOS processes while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent employs a nested structure where the pull-up transistor is effectively nested above the pull-down transistor, sharing common source/drain regions. This nesting arrangement maximizes the use of available space and enables higher integration density without complicating the manufacturing process.
Data Source
AI summary
Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.