Integrated Sub-Block Interleaving and Rate Matching for LTE
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LTE systems face challenges in meeting timing requirements due to the need for significant processing time and memory resources for sub-block interleaving and rate matching, especially when simulating multiple user devices, leading to delays and inefficiencies in uplink processing.
Innovation Solution
An integrated sub-block interleaving and rate matching system that uses a buffer memory and a rate matching module to transfer data according to an interleaving algorithm, eliminating the need for separate sub-block interleavers and post-interleave buffers, allowing for real-time address computation and reduced memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate sub-block interleavers and post-interleave buffers are used for LTE uplink processing, then data processing completeness is ensured, but processing time increases and hardware complexity increases
Solution Approach 1:
The patent combines the sub-block interleaver and rate matcher into a single integrated module that performs both functions simultaneously. The interleaving and rate matching operations are executed in one pass through the encoded data, eliminating the need for separate processing stages and reducing overall processing time while maintaining data processing completeness
Solution Approach 2:
The integrated module serves multiple functions: it performs sub-block interleaving, rate matching, and handles the interaction between these operations. By making the module multi-functional, the patent eliminates the need for separate dedicated hardware blocks for each function, thereby reducing hardware complexity and processing time
2Manufacturing precision
If separate sub-block interleavers and post-interleave buffers are used, then processing accuracy is maintained, but hardware complexity increases
Solution Approach 1:
The patent merges the sub-block interleaver and rate matcher into a single integrated module. This consolidation reduces the number of separate hardware blocks needed in the system, thereby reducing hardware complexity while maintaining processing accuracy through careful design of the integrated operations
Solution Approach 2:
The integrated module is designed to perform multiple functions (interleving, rate matching, and coordinating between them) within a single hardware block. This multi-functionality reduces the overall hardware complexity by eliminating redundant components while preserving the accuracy of each individual processing function
3Reliability
If conventional separate processing blocks are used, then processing thoroughness is ensured, but memory usage increases
Solution Approach 1:
By combining the interleaver and rate matcher into one module, the patent eliminates the need for separate buffer memories for each processing stage. The integrated design allows data to be processed in-place or with minimal buffering, significantly reducing overall memory usage while ensuring processing thoroughness through coordinated operations
Data Source
AI summary
Methods, systems, and computer readable media for fast, reduced memory and integrated sub-block interleaving and rate matching are disclosed. According to one aspect, the subject matter described herein includes a system for integrated sub-block interleaving and rate matching, which includes a buffer memory for storing sub-block data that has been encoded according to a channel encoding algorithm and a rate matching module for reading the sub-block data from the buffer memory using a sequence of addresses according to an interleaving algorithm, such that data is transferred from the buffer memory to the rate matching module in an order that emulates the order that the data would be produced by the interleaving algorithm or in the order that the data would be produced by the interleaving algorithm as modified by a rate matching algorithm.