Integrated Substrate Structure for Multi-Chip Routing and Heat Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor substrate technologies face challenges in manufacturing large-format substrates for multiple chip integration due to high costs and yield issues, and they lack effective heat dissipation features to manage increasing power dissipation requirements in integrated circuit structures.
Innovation Solution
An integrated substrate structure is developed, comprising a coarse redistribution structure with a coarse dielectric layer and circuitry, fine redistribution segments with finer pitch and denser circuitry, and conductive connectors interposed between them, along with heat-dissipating features and underfill layers for enhanced mechanical strength and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a larger substrate is used to accommodate multiple chips, then the substrate area increases, but the manufacturing cost increases and yield decreases
Solution Approach 1:
The substrate is divided into multiple standard-sized substrate sections that can be manufactured separately using conventional processes. These sections are then interconnected through redistribution circuits to form a large-format integrated substrate structure, enabling multiple chips to be mounted while avoiding the yield and cost issues of manufacturing a single large substrate.
Solution Approach 2:
Multiple standard substrate sections are nested or assembled together to create a larger integrated substrate structure. The redistribution circuits are embedded within this nested structure to provide electrical interconnection between the sections, effectively creating a large substrate from smaller, easier-to-manufacture components.
2Productivity
If IC structure functionality increases and size shrinks, then integration density improves, but power dissipation increases
Solution Approach 1:
The integrated substrate structure divides the substrate into multiple sections with redistribution circuits that can route power and signal paths. This segmentation allows for better thermal management by distributing power dissipation across multiple sections rather than concentrating it in a single shrunk IC structure.
Solution Approach 2:
The patent employs multi-layer redistribution circuits with conductive patterns in different layers (first layer, second layer, third layer) connected through conductive vias. This three-dimensional routing approach allows power and signals to be distributed through multiple dimensions, reducing thermal concentration and improving heat dissipation while maintaining high integration density.
Data Source
AI summary
An integrated substrate, an electronic assembly, and manufacturing methods thereof are provided. The integrated substrate structure includes a coarse redistribution structure, fine redistribution segments, and conductive connectors. The coarse redistribution structure includes a coarse dielectric layer and a coarse circuitry embedded therein. The fine redistribution segments disposed over the coarse redistribution structure and disposed side by side and apart from one another. The respective fine redistribution segment includes a fine dielectric layer thinner than the coarse dielectric layer, and a fine circuitry embedded in the fine dielectric layer. The fine circuitry includes a dimension and a pitch finer than those of the coarse circuitry, and a layout density of the fine circuitry is denser than that of the coarse circuitry. The conductive connectors are interposed between the coarse redistribution structure and the fine redistribution segments, and the coarse circuitry is electrically coupled to the fine circuitry through the conductive connectors.