Integrated Power Switch Layout for Low Loop Inductance
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Solution Overview
Problem
High parasitic loop inductance in switching circuits leads to large voltage spikes and increased switching loss, potentially causing switch breakdown during commutation.
Innovation Solution
An integrated switch device is designed by integrating multiple switches on a single semi-conductive substrate, with channels formed in close proximity and optionally a trench between them, and additional parallel gates and drains to reduce loop inductance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If multiple switches are integrated on a single semi-conductive substrate in close proximity, then loop inductance is reduced, but device complexity increases
Solution Approach 1:
Multiple switches are integrated on a single semi-conductive substrate with their channels formed in close proximity, merging multiple switching functions into one compact device. This integration reduces the loop area and consequently minimizes parasitic loop inductance while maintaining individual switch functionality through separate gate controls.
Solution Approach 2:
The patent utilizes vertical stacking of multiple switches on the semi-conductive substrate, transitioning from a planar arrangement to a three-dimensional configuration. This dimensional change allows multiple channels to occupy close proximity without excessive lateral spacing, reducing loop inductance while managing device complexity through vertical integration.
2Object-affected harmful factors
If channels are formed in close proximity, then loop inductance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Multiple switch channels are merged into a single integrated structure on the semi-conductive substrate, with their paths formed in close proximity. This merging reduces the overall loop area and minimizes parasitic inductance, while the unified fabrication process maintains manufacturing precision through standardized processing techniques.
3Object-affected harmful factors
If additional parallel gates and drains are added, then loop inductance and resistance are reduced, but device complexity increases
Solution Approach 1:
Each switch is segmented into distinct gate and drain regions that are arranged in parallel configurations. This segmentation allows multiple current paths to be formed within the integrated structure, reducing overall loop inductance and resistance while maintaining manageable device complexity through modular design elements.
Solution Approach 2:
The integrated switch device provides multiple functions within a single structure, with parallel gates and drains enabling simultaneous switching operations. This multi-functionality reduces parasitic parameters while the universal substrate design manages complexity by accommodating various switching configurations.
Data Source
AI summary
An integrated power switch and a method of operating such a switch is disclosed. The integrated power switch may include a source, one or more first drains, and one or more second drains formed on a semi-conductive substrate. Channels may be formed between the source and the plurality of first and second drains. The integrated power switch may further include one or more gates coupled to the first and second channels. Capacitance may be formed by the spatial proximity of the first and second channels, and as a result, a loop inductance may be reduced.