Integrated TSV and RDL Fabrication via Unified Resist Patterning
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Solution Overview
Problem
Current methods for fabricating through-silicon vias and redistribution layers in 3D ICs require multiple patterning processes and masks, leading to extended cycle times and reduced throughput.
Innovation Solution
A method involving the formation of through-silicon holes, patterned resist with openings for redistribution layers, and sequential electrochemical deposition steps to create conductive layers for both through-silicon vias and redistribution layers in a single structure, allowing for simultaneous formation without overfilling or underfilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes and masks are used to fabricate through-silicon vias and redistribution layers separately, then the fabrication precision and reliability are improved, but the manufacturing time and process complexity increase significantly
Solution Approach 1:
The patent combines the formation of through-silicon vias and redistribution layers into a single electrochemical deposition process. By using a unified resist pattern that defines both TSV and RDL locations, and performing sequential deposition steps in one process flow, the method merges two previously separate fabrication sequences into one integrated process, thereby reducing manufacturing time while maintaining precision
Solution Approach 2:
The patent performs preliminary patterning of the resist layer to define both TSV openings and RDL patterns before deposition begins. This preliminary action establishes the complete geometric framework for both structures in advance, allowing subsequent deposition steps to form both TSVs and RDLs simultaneously without requiring intermediate patterning steps, thus reducing overall manufacturing time
2Manufacturing precision
If multiple patterning processes and masks are used to fabricate through-silicon vias and redistribution layers separately, then the fabrication precision and reliability are improved, but the process complexity increases significantly
Solution Approach 1:
The patent merges multiple separate patterning and deposition processes into a single integrated electrochemical deposition process. By using one unified resist pattern to define both TSV and RDL features, and performing sequential deposition in one process flow, the method reduces the number of process modules from multiple separate steps to one consolidated process sequence, thereby reducing process complexity
Solution Approach 2:
The unified resist pattern serves multiple functions simultaneously: it defines the locations of through-silicon via openings, defines the locations of redistribution layer patterns, and provides the geometric template for both structures during deposition. This multi-functionality eliminates the need for separate masks and patterning processes for TSVs and RDLs, reducing process complexity
3Productivity
If sequential electrochemical deposition steps are used to form conductive layers for both through-silicon vias and redistribution layers, then the productivity is improved, but the manufacturing precision may be compromised due to potential overfilling or underfilling
Solution Approach 1:
The patent employs periodic, sequential electrochemical deposition steps with distinct duration periods. The first deposition step runs for a controlled time to fill TSV openings to a specific level, then stops before filling RDL openings. The second deposition step continues the process to complete the RDL formation. This periodic control of deposition timing ensures precise thickness management and prevents overfilling or underfilling, maintaining manufacturing precision while achieving high productivity
Solution Approach 2:
The patent uses partial deposition action in the first electrochemical deposition step, where deposition is performed for a duration sufficient to fill TSV openings but intentionally stopped before completely filling RDL openings. This partial action allows selective filling of different structures at different stages, enabling precise control over conductive layer thickness and geometry without requiring excessive deposition time that would compromise precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and time required for fabrication, improving throughput by enabling the formation of integrated structures with efficient interconnections and routing, while maintaining uniformity and minimizing thickness loading effects.
Implementation Method 1
performing a first electrochemical deposition (ECD) process step and a second ECD process step to fill the through-silicon hole; and performing a third ECD process step to till the at least one opening and the at least another opening in the pattern resist
Data Source
AI summary
A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.