Integrated Vertical Lateral Semiconductor Devices Crosstalk Isolation
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Solution Overview
Problem
The integration of vertical and lateral MOSFET devices in a common semiconductor die is challenging due to substantial differences in breakdown voltages, leading to crosstalk and interference, making it difficult to produce compact, efficient integrated devices for both power and logic applications.
Innovation Solution
The integration of vertical and lateral MOSFET devices on a common semiconductor die is achieved by using a common epitaxial layer with different implantation levels and a high-energy implant process to adjust breakdown voltages, along with a blocking implant and insulation structures to isolate the devices, allowing for compact, high-voltage/low-voltage, and digital/analog applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical and lateral MOSFET devices are integrated on a common semiconductor die, then device integration and compactness are improved, but crosstalk and interference between devices increase due to substantial differences in breakdown voltages
Solution Approach 1:
The patent applies local quality by creating different implantation regions within the semiconductor die. A first implantation region is formed for the vertical MOSFET with a first breakdown voltage, and a second implantation region is formed for the lateral MOSFET with a second breakdown voltage. This allows each device to have optimized local electrical properties suitable for its specific function while coexisting on the same die, thereby reducing crosstalk and interference between devices with different voltage requirements.
Solution Approach 2:
The patent segments the semiconductor die into distinct implantation regions with different electrical characteristics. By dividing the die into a first implantation region for vertical MOSFETs and a second implantation region for lateral MOSFETs, each segment can operate at its optimal breakdown voltage without interfering with the other segment, thus enabling integrated operation while minimizing harmful interactions.
2Adaptability or versatility
If different breakdown voltages are used for vertical and lateral MOSFETs, then device functionality for both power and logic applications is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs parameter changes by varying the implantation energy and dosage parameters for different regions of the semiconductor die. A first ion implantation is performed with parameters optimized for vertical MOSFETs to achieve a first breakdown voltage, and a second ion implantation is performed with different parameters to achieve a second breakdown voltage for lateral MOSFETs. This allows the manufacturing process to produce devices with different electrical characteristics using controlled variations in implantation parameters, enabling both power and logic applications on the same die.
3Manufacturing precision
If high-energy implant process is used to adjust breakdown voltages, then voltage control precision is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing ion implantation processes during the semiconductor fabrication sequence to pre-establish the desired breakdown voltage characteristics before final device assembly. The first ion implantation adjusts the breakdown voltage of vertical MOSFETs, and the second ion implantation adjusts the breakdown voltage of lateral MOSFETs, ensuring that voltage control is built into the device structure during manufacturing rather than requiring post-fabrication adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, integrated semiconductor dies that can handle both high-power and low-power applications with reduced parts and simpler design, minimizing crosstalk and interference between vertical and lateral devices.
Implementation Method 1
The formation of the first MOSFET may include the application of a high-energy implant process in a first portion of an epitaxial layer of the semiconductor die
Implementation Method 2
The formation of the second MOSFET may include the formation of a blocking implant above a second portion of the epitaxial layer
Data Source
AI summary
An integrated circuit die that may have one vertical transistor and one horizontal transistor is disclosed. The transistors may have substantially different breakdown voltages. The vertical transistor may be used in power circuitry applications and the horizontal transistor may be used in logic circuitry applications.