Integrated Bottom Via Electrode for Uniform FTJ Memory Cells
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Solution Overview
Problem
The manufacturing process for ferroelectric tunnel junction (FTJ) devices in non-volatile memory, such as FeRAM, faces challenges due to high variability in the surface uniformity of conductive layers, leading to degraded remanent polarization and increased fabrication costs, which affects yield and reliability.
Innovation Solution
A method is introduced to form a bottom via and bottom electrode using a single conductive layer, where a planarization process is reduced to minimize costs and time while maintaining surface uniformity, allowing the conductive layer to function as both a via and electrode, thereby simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate bottom via and bottom electrode structures are used, then electrical connection and electrode function are achieved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent combines the bottom via and bottom electrode into a single integrated conductive structure. The conductive layer is patterned to form a bottom electrode that directly extends into an opening in the dielectric layer, eliminating the need for a separate bottom via structure. This integration maintains electrical connection reliability while reducing device complexity and manufacturing steps.
Solution Approach 2:
The conductive layer serves dual functions: it acts as the bottom electrode for the ferroelectric tunnel junction and simultaneously provides the electrical connection function previously requiring a separate via. This multi-functional design simplifies the overall device architecture while maintaining both electrode and connection capabilities.
2Reliability
If multiple conductive layers are deposited for bottom via and bottom electrode, then functional separation is achieved, but manufacturing time and costs increase
Solution Approach 1:
The patent deposits a single conductive layer that is then patterned to form both the bottom electrode and the electrical connection structure. This eliminates the need for multiple sequential deposition processes, reducing manufacturing time and costs while maintaining the functional performance required for reliable device operation.
Solution Approach 2:
The single conductive layer is segmented through patterning to create distinct functional regions: the bottom electrode area and the connection area extending into the opening. This segmentation achieves functional separation without requiring multiple deposition steps, improving fabrication efficiency.
3Manufacturing precision
If extensive planarization is performed on conductive layers, then surface uniformity is improved, but process time and costs increase
Solution Approach 1:
The patent applies planarization selectively and minimally to the conductive layer, performing it only where necessary to achieve adequate surface uniformity for subsequent ferroelectric layer deposition. This partial application of planarization maintains sufficient surface quality while avoiding the excessive processing time and costs associated with extensive planarization of entire conductive layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process time and costs, maintains high surface uniformity, and enhances the reliability of ferroelectric segment properties without sacrificing functionality, leading to improved fabrication efficiency and yield.
Implementation Method 1
performing a planarization into the first conductive layer to flatten a top of the first conductive layer
Data Source
AI summary
Some embodiments relate to a method of forming an integrated chip, including forming a first wire level over a substrate; depositing an etch stop layer over the first wire level; etching the etch stop layer to form an opening over the first wire level; depositing a barrier layer over the etch stop layer, the barrier layer extending into the opening; depositing a first conductive layer over the barrier layer and in the opening; performing a planarization into the first conductive layer to flatten a top of the first conductive layer, wherein the planarization stops before reaching the barrier layer; depositing a data storage layer and a second conductive layer over the first conductive layer; and patterning the barrier layer, the first conductive layer, the data storage layer, and the second conductive layer to form a memory cell at the opening.