Integrated Voltage Regulator Partitioning for Fast Transient Response
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Solution Overview
Problem
Existing power delivery systems face challenges in efficiently managing power distribution to loads with increased power needs, requiring improved control schemes to regulate voltage and manage transient power requirements effectively.
Innovation Solution
A system with a substrate integrating a load circuit and a power delivery circuit, where the power delivery circuit includes error management and switch control circuits to generate error signals and control power switches, optimizing voltage regulation across multiple phases, and utilizing a communication bus for fast communication between chips to adjust voltage quickly and efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If power delivery circuits are integrated on the same chip as load circuits, then parasitics and delays are reduced, but device complexity increases
Solution Approach 1:
The power delivery circuit is divided into two separate chips: a first chip containing the load circuit and error management circuit, and a second chip containing the power delivery circuit with voltage generator. This segmentation allows integration benefits on each chip while managing overall system complexity through modular architecture.
Solution Approach 2:
A communication bus serves as an intermediary between the first chip and second chip, enabling fast signal transmission for error signals and control data. This intermediary connection reduces delays compared to traditional external connections while maintaining manageable device complexity through standardized interfaces.
2Device complexity
If power delivery circuit is separated from load circuit onto different chips, then device complexity is reduced, but parasitics and delays increase
Solution Approach 1:
The communication bus acts as a high-speed intermediary connection between the separately integrated first chip and second chip, minimizing signal delays despite physical separation. This allows each chip to be optimized independently while maintaining fast response times through dedicated communication pathways.
Solution Approach 2:
The error management circuit on the first chip and power delivery circuit on the second chip are functionally merged through tight coupling via the communication bus, achieving coordinated control that compensates for physical separation and reduces effective signal delay.
3Adaptability or versatility
If multiple phases are used for power delivery, then power management capability is improved, but control complexity increases
Solution Approach 1:
The power delivery circuit is designed to handle multiple phases through a unified voltage generator and control architecture, allowing the same circuitry to serve multiple power delivery functions simultaneously, thereby improving power management capability without proportionally increasing control complexity.
Solution Approach 2:
The error management circuit continuously monitors power delivery conditions and provides feedback through the communication bus to adjust the voltage generator output, enabling adaptive multi-phase power management with automated control that reduces the burden on external control schemes.
Data Source
AI summary
A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.