Integrated VRM Package Layout for Compact SoC Power Delivery
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Solution Overview
Problem
Existing techniques for packaging voltage regulators in mobile devices face challenges in integrating passive components like inductors and capacitors with System-on-a-Chip (SoC) manufacturing processes, leading to increased footprint and inefficiencies.
Innovation Solution
A system package is proposed that includes a voltage regulator module with a controller die, interconnect regions with conductive paths, and passive circuit elements like inductors and capacitors, which are fabricated separately and integrated in a common package to minimize footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If passive components are manufactured separately from the SoC, then manufacturing flexibility is improved, but device footprint increases
Solution Approach 1:
The patent merges the voltage regulator module (containing passive components like inductors and capacitors) with the SoC into a single integrated package. The controller die is coupled to passive circuit elements through conductive paths within the same package, eliminating the need for separate discrete component mounting and reducing overall device footprint while maintaining manufacturing flexibility through modular integration.
2Area of stationary object
If voltage regulators are integrated into the SoC, then device compactness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the voltage regulator system into distinct functional modules: a controller die containing active regulation circuitry, and separate passive circuit elements (inductors, capacitors). These segments are manufactured using optimized processes for each component type, then integrated through a standardized interconnect structure with conductive paths, reducing overall manufacturing complexity compared to fully monolithic integration.
3Reliability
If passive components are integrated in a common package, then power supply stability is improved, but interconnection complexity increases
Solution Approach 1:
The patent introduces an interconnect structure with multiple conductive paths as an intermediary between the controller die and passive circuit elements. This intermediary provides standardized, low-inductance connection pathways that ensure stable power delivery while managing interconnection complexity through systematic routing and attachment structures, reducing parasitic effects and improving power supply stability.
Data Source
AI summary
A disclosed system includes a package body that includes a system-on-a-chip (SoC) and an interconnect region. In an embodiment, the interconnect region includes a first conductive path between the SoC and a voltage regulator module (VRM), a second conductive path between the SoC and a first external connection, and a third conductive path between the VRM and a second external connection. In another embodiment, the VRM is positioned between and coupled to a first portion of the SoC and a first surface of the interconnect region. A second portion of the SoC is coupled directly to the first surface of the interconnection region. In another embodiment, the interconnect region has first and second opposing surfaces. The SoC is positioned on the first surface of the interconnect region. The VRM is externally coupled to a first surface of the package body adjacent to the second surface of the interconnect region.