Integrated Wake-Up Receiver Power Reduction
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Solution Overview
Problem
Existing wake-up receivers in wireless systems face challenges such as high power consumption, bulky and expensive external components, limited integration due to old CMOS processes, and lack of standardization, which hinder their efficiency and form factor in achieving low power and low latency.
Innovation Solution
A fully-integrated ultra-low power wake-up receiver design that includes a mixer, switched-capacitor multiplier, amplifier, and integrated filter, leveraging scaled CMOS processes and eliminating the need for external high-Q components, with a clock source and analog-to-digital converter to detect wake-up signals compliant with IEEE 802.11 standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external high-Q components (filters, crystal oscillators) are used in wake-up receivers, then frequency selectivity and signal detection accuracy are improved, but device size, cost, and integration difficulty increase
Solution Approach 1:
The patent merges the functions of external filters and crystal oscillators into integrated on-chip components. Specifically, it uses on-chip inductors and capacitors to implement bandpass filters, and integrates clock generation directly on the CMOS chip, eliminating the need for separate external high-Q components while maintaining signal detection accuracy
Solution Approach 2:
The patent changes the physical parameters of on-chip passive components (inductors and capacitors) to achieve high-Q performance. By optimizing the inductance values and capacitance values within the CMOS process capabilities, the system achieves sufficient frequency selectivity without requiring external components
2Loss of time
If the main receiver is kept always on to reduce latency, then response time is improved, but power consumption increases
Solution Approach 1:
The patent segments the receiver functionality into two independent parts: a simple always-on wake-up receiver that detects wake-up signals, and a main receiver that processes actual data. The wake-up receiver has a simplified architecture without complex baseband processing, allowing it to operate at very low power while the main receiver remains in low-power mode until activated
Solution Approach 2:
The wake-up receiver acts as an intermediary component that bridges the gap between always-on operation and low-power mode. It continuously monitors for wake-up signals and triggers the main receiver only when necessary, thereby reducing overall system latency while maintaining low power consumption during idle periods
3Ease of manufacture
If older CMOS processes are used for wake-up receiver integration, then manufacturing simplicity is maintained, but integration capability and performance are limited
Solution Approach 1:
The patent exploits the parameter improvements available in scaled CMOS processes (65nm and below). By utilizing the higher transistor density, lower capacitance, and improved frequency characteristics of modern CMOS processes, the system achieves better performance and integration capability while maintaining compatibility with standard manufacturing processes
Data Source
AI summary
An apparatus is provided which comprises: a mixer to mix a first signal of a first frequency with a second signal of a second frequency, and to generate a first output; a switched-capacitor multiplier, coupled to the mixer, to receive the first output and to provide a second output with reduced noise; and an amplifier, coupled to the switched-capacitor multiplier, to amplify the second output.