Integrating ADC Timing Using DLL Delay Cells
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Solution Overview
Problem
Existing analog to digital converters (ADCs) face accuracy issues due to process and temperature variations, particularly in designs using digital delay lines, which affect the precision of the timing reference required for high-resolution signal conversion.
Innovation Solution
The use of a Delay Locked Loop (DLL) or ring oscillator with a delay line, where the delay locked loop is synchronized with a reference clock signal or the oscillation frequency is calibrated to reduce the impact of process and temperature variations, allowing for accurate timing measurements and high-resolution sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high precision timing reference operating at a frequency many times higher than the sampling rate is used to achieve high resolution, then the resolution is improved, but the device complexity and power consumption increase significantly
Solution Approach 1:
The patent changes the operating frequency parameter of the timing reference from a high frequency (many times the sampling rate) to a lower frequency (equal to or greater than the sampling rate). This is achieved by using an integrating ADC architecture where the timing reference operates at a reduced frequency while still achieving high resolution through the integration process, thereby reducing device complexity and power consumption.
2Ease of manufacture
If digital delay lines are used to reduce implementation cost, then the ease of manufacture is improved, but the accuracy deteriorates due to process and temperature variations
Solution Approach 1:
The patent introduces a feedback mechanism where the timing measurement from the delay line is used to adjust and compensate for process and temperature variations. The system continuously monitors the timing reference accuracy and applies corrections to maintain high accuracy despite environmental variations, while still using the cost-effective digital delay line implementation.
3Measurement precision
If the timing reference frequency is increased to achieve higher resolution, then the measurement precision is improved, but the power consumption increases
Solution Approach 1:
The patent changes the frequency parameter of the timing reference from a high value to a lower value (equal to or greater than sampling rate only). The integrating ADC architecture allows this frequency reduction while maintaining high resolution by accumulating timing information over multiple cycles through the integration process, thereby significantly reducing power consumption.
4Measurement precision
If a high frequency timing reference is used to achieve high resolution, then the measurement precision is improved, but the device operates less reliably under process and temperature variations
Solution Approach 1:
The patent implements feedback mechanisms that continuously monitor and compensate for process and temperature variations affecting the timing reference. This feedback control maintains the accuracy and reliability of the timing measurement despite environmental variations, allowing the system to operate reliably at lower frequencies without sacrificing resolution.
Data Source
AI summary
An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number.