Integrating A/D Converter With TDC Phase Latching for Higher Resolution

The patent divides the resolution enhancement into two independent segments: (1) higher-order bits obtained by counting clock cycles in the comparator, and (2) lower-order bits obtained by measuring the phase position within the clock cycle using the delay circuit. This segmentation allows each segment to be optimized independently, with the phase measurement segment providing fine-grained resolution without requiring increased clock frequency, thereby avoiding the current consumption penalty.

The patent transitions from a one-dimensional resolution approach (increasing clock frequency to increase count) to a two-dimensional approach by introducing phase information as an additional dimension. The delay circuit measures the phase position of the clock signal, effectively adding a temporal dimension within each clock cycle. This allows resolution enhancement without increasing the clock frequency, as the phase measurement provides sub-cycle precision.

The patent segments the conversion process into two independent parallel paths: (1) higher-order bit determination through clock cycle counting, and (2) lower-order bit determination through phase position measurement. Both paths operate simultaneously within the same conversion period, eliminating the need to extend the conversion period for higher resolution. This maintains the original conversion period duration, thereby preserving the frame rate.

The patent maintains continuous operation throughout the conversion period by performing both higher-order and lower-order bit determination simultaneously. The delay circuit continuously measures phase position while the counter simultaneously counts clock cycles, ensuring that the full conversion period is productively utilized. This parallel continuous operation achieves high resolution without extending the conversion period, thus maintaining high frame rate.

The patent merges the phase measurement function into the existing comparator structure by integrating the delay circuit within the comparator block. Instead of distributing multiple phase-shifted clocks to separate A/D converters, the single clock signal is fed to both the counter and the delay circuit, which generates the delayed signals internally. This merging approach achieves phase-based resolution enhancement while avoiding the complexity of multiple clock distribution networks.

The delay circuit serves multiple functions: it generates delayed clock signals for phase measurement, provides timing references for the conversion process, and enables sub-cycle resolution measurement. By making the delay circuit multi-functional, the patent avoids adding dedicated separate circuits for each function, thereby reducing overall device complexity while achieving high resolution through phase information.