Integrator Ramp Generator Using DAC Polarity Switching to Cut kTC Noise
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Solution Overview
Problem
Single-slope analog-to-digital converters face challenges in minimizing kTC noise from resetting sampling capacitors, which requires smaller capacitors to maintain a capacitance ratio, leading to matching issues affecting non-linear ramp performance, and using a 10-bit DAC is inefficient in terms of real estate and power consumption.
Innovation Solution
A ramp generator incorporating an 8-bit DAC with a polarity reversing switch and an integrator circuit, coupled with sampling capacitors, to generate decrementing and incrementing ramp signals, minimizing kTC reset noise by resetting capacitors only four times and allowing a larger capacitance ratio, thus optimizing space and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If sampling capacitors are reset frequently to minimize kTC noise, then kTC reset noise is reduced, but the capacitance ratio must be kept small which leads to matching issues and degraded non-linear ramp performance
Solution Approach 1:
The patent implements periodic resetting of sampling capacitors at specific intervals during the conversion cycle, rather than continuous or frequent resetting. This periodic action minimizes kTC noise while avoiding the need for small capacitance ratios, thus preventing matching issues and maintaining non-linear ramp performance.
2Measurement precision
If a 10-bit DAC is used to generate the ramp waveform, then the ADC resolution is achieved, but the real estate and power consumption increase significantly
Solution Approach 1:
The patent segments the DAC functionality by using separate DACs for different portions of the conversion range. Instead of a single 10-bit DAC, multiple smaller DACs (e.g., two 5-bit DACs) are used to cover the full range, significantly reducing the circuit area and power consumption while maintaining the required 10-bit resolution.
3Object-affected harmful factors
If a smaller capacitance ratio is used to minimize kTC noise, then kTC reset noise is reduced, but the circuit precision for non-linear ramp performance deteriorates
Solution Approach 1:
The patent uses periodic resetting of capacitors at optimized intervals, allowing the use of larger capacitance ratios that improve non-linear ramp performance while still effectively minimizing kTC noise through the timing and frequency of the periodic reset operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces kTC reset noise and allows for a larger capacitance ratio, enhancing non-linear ramp performance while significantly reducing the circuit size and power consumption compared to a 10-bit DAC, thereby optimizing ADC performance.
Implementation Method 1
a sampling capacitor, an integrator circuit
Implementation Method 2
an integrator circuit... The time it takes for the waveform to exceed the analog input voltage level is measured
Data Source
AI summary
A ramp generator includes a digital-to-analog converter (DAC), a sampling capacitor, an integrator circuit, a polarity reversing switch selectively coupling first and second outputs of the DAC to a first side of the sampling capacitor, a first switch coupling a second side of the sampling capacitor to a reference voltage source, and a second switch coupling the second side of the sampling capacitor to an input of the integrator circuit.