Integrity Manager Message Synchronization for Mixed-Mode Processors
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Solution Overview
Problem
Current solutions for achieving data integrity in aircraft computer systems using processor units are inefficient, as they often require customized architectures and do not effectively handle single-core or multi-core processors, leading to issues with data accuracy and redundancy across different processor types.
Innovation Solution
A message management system with an integrity manager that operates in mixed integrity modes, ensuring redundantly calculated outputs from processor units match by aligning timing and synchronizing messages between processor units and an external node, regardless of processor type or architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If customized processor architectures are used to achieve data integrity, then reliability is improved, but device complexity increases
Solution Approach 1:
The integrity manager is designed as a universal component that can manage data integrity across different processor types (single core, multiple cores, heterogeneous cores) without requiring customized architectures for each processor type. This multi-functional design allows the same integrity manager to serve various processor configurations, reducing overall system complexity while maintaining reliability.
Solution Approach 2:
The integrity manager acts as an intermediary component between processor units and external nodes, centralizing the integrity management function. This mediator approach allows different processor types to interact with the integrity manager through standardized interfaces, eliminating the need for processor-specific customized architectures and reducing device complexity.
2Device complexity
If single core processor units are used, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The system segments processor units into different types (single core and multiple core) and allows each to operate independently while maintaining compatibility through the integrity manager. This segmentation enables the system to utilize simpler single core processors for tasks where they are sufficient, while deploying more powerful multiple core processors only when needed, optimizing the balance between complexity and productivity.
Solution Approach 2:
The integrity manager dynamically adapts its behavior based on the processor type and operational mode (e.g., lockstep mode for single core, diverse mode for multiple core). This dynamic adjustment allows the system to optimize productivity for each processor type while maintaining a unified management approach, preventing the need for overly complex fixed architectures.
3Productivity
If multiple core processor units are used, then productivity is improved, but device complexity increases
Solution Approach 1:
The integrity manager implements different integrity management strategies for different processor configurations (e.g., lockstep mode for single core processors, diverse mode for multiple core processors). This local quality approach allows the system to optimize for each processor type's specific characteristics without requiring a completely different architecture for each type, managing complexity through targeted differentiation.
4Reliability
If lockstep mode is used for single core processors, then reliability is improved, but productivity decreases
Solution Approach 1:
The system dynamically switches between lockstep mode and diverse mode based on the processor configuration and operational requirements. For single core processors, lockstep mode can be enabled when maximum reliability is needed, while diverse mode is used for multiple core processors or when processing efficiency is prioritized. This dynamic adaptation allows the system to optimize the balance between reliability and productivity for each specific context.
Data Source
AI summary
A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.