Integrity Tree Cache Locking to Prevent Memory Access Deadlock

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Solution Overview

Problem

Existing memory integrity confirmation methods using integrity trees face the risk of deadlock due to collisions in update processing when parallel accesses occur, leading to incomplete processing and blocked caches.

Innovation Solution

A memory integrity confirmation device and method that employs a tree cache with a request processing unit to lock intermediate nodes and register wait requests, using a registration unit to manage search requests and block them based on the number of registered wait requests, preventing deadlock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If locking mechanism is used to control parallel access to intermediate nodes, then collision in update processing is avoided, but deadlock occurs due to blocked processing

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-allocating multiple MSHR entries for each intermediate node before access conflicts occur. When an intermediate node is accessed, multiple MSHR entries are reserved in advance, allowing parallel requests to be queued without blocking the entire processing pipeline. This prevents deadlock while maintaining data integrity through controlled access.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the MSHR resource into multiple entries that can be independently allocated to different requests accessing the same intermediate node. Instead of treating the lock as a single monolithic resource, the MSHR is divided into multiple slots, allowing fine-grained parallel processing while maintaining coordination between concurrent accesses to the same node.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If MSHR is used to lock intermediate nodes, then exclusive control is achieved, but processing series cannot be completed and deadlock occurs

Engineering Contradiction:
Improvenode access controlVSAvoidprocessing completion time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The system performs preliminary action by pre-reserving multiple MSHR entries for each intermediate node before actual access conflicts arise. This allows the system to maintain exclusive control through the MSHR lock mechanism while having capacity pre-prepared to handle multiple parallel requests without causing processing series to stall or deadlock.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The MSHR structure acts as an intermediary between the lock mechanism and the processing units. By introducing multiple MSHR entries as intermediate buffers, the system can coordinate access to intermediate nodes without creating direct blocking relationships that lead to deadlock, allowing processing series to complete while maintaining operational simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260066029A1Memory integrity confirmation device, information processing device, and memory integrity confirmation method
Publication Date: 2026.03.05 NEC CORP
  • US20260066029A1 patent drawing
  • US20260066029A1 patent drawing
  • US20260066029A1 patent drawing

AI summary

Provided are a memory integrity confirmation device capable of preventing occurrence of deadlock. The memory integrity confirmation device includes a tree cache that temporarily stores data allocated to a node in an integrity tree including nodes arranged in a tree shape, and a request processing unit that receives a request for a leaf node in the integrity tree from the cache memory and requests the tree cache to search for an intermediate node from the leaf node to a root node in the integrity tree, in which the tree cache locks the intermediate node for exclusively controlling a request for searching for the same intermediate node and includes a first registration unit that registers a wait request for each locked intermediate node, and the request processing unit includes a first block unit that blocks a request accepted by the request processing unit.