Intelligent Bit Line Precharge for SRAM Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM architectures consume significant dynamic power due to the precharging and discharging of both bit lines in each write cycle, which is wasteful when the binary value remains unchanged, leading to inefficient power management in mobile devices.
Innovation Solution
An intelligent write driver that only changes the precharge state of bit lines in a bit line pair when the current data bit differs from the previous bit, maintaining the previous state if the data bits are the same, thereby reducing unnecessary charging and discharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both bit lines in a bit line pair are precharged for each write cycle, then the SRAM is prepared for any possible write operation, but dynamic power consumption increases significantly due to unnecessary precharging and discharging
Solution Approach 1:
The patent applies dynamics by making the precharge state configurable and adaptable based on the actual write data being written. Instead of a fixed precharge-to-high state, the system dynamically adjusts bit line precharge states to match the required write operation, enabling precharge-to-high or precharge-to-low based on whether the write data is logic high or logic low respectively. This eliminates unnecessary precharging and discharging cycles, reducing dynamic power consumption while maintaining write operation reliability.
Solution Approach 2:
The patent changes the parameter of bit line precharge voltage state from a fixed high state to a variable state that can be either high or low depending on the write data. The write driver circuit responds to write data to selectively precharge bit lines to appropriate states, and the differential write driver further optimizes this by adjusting the precharge voltage levels based on the differential write data signals. This parameter adaptation resolves the contradiction by ensuring precharge operations only occur when necessary.
2Ease of operation
If the precharge state is changed for every write cycle, then the bit lines are always ready for any data value, but power is wasted when the data bit remains unchanged
Solution Approach 1:
The patent extracts and eliminates the unnecessary precharge operation from the write cycle when the write data matches the current bit line state. By comparing the write data with the current precharge state, the system identifies and removes redundant precharge and discharge operations, keeping only the essential ones required for actual state changes. This extraction of unnecessary operations reduces power consumption while maintaining operational flexibility.
Solution Approach 2:
The patent implements feedback by having the write driver circuit monitor the write data and the current bit line precharge state, and use this information to determine whether precharging is necessary. The differential write driver uses differential signaling to provide feedback about the required write operation, enabling the circuit to intelligently adjust precharge behavior. This feedback mechanism ensures precharge operations occur only when needed, resolving the contradiction between operational flexibility and power efficiency.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.