Intelligent Fabric Chip for Low Latency Sensor Data Transport

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Solution Overview

Problem

System-on-chip (SoC) designers face challenges in managing interconnect architectures for tens or hundreds of Intellectual Property blocks, leading to increased wire delays and latency, particularly in real-time sensor data transport across embedded environments, where instantaneous analog-to-digital conversion can overwhelm processors and networks.

Innovation Solution

An intelligent fabric chip with a soft application processor, reconfigurable hardware intelligent processor, and partitioned memory storage, along with an interface to an external reconfigurable communication processor, which implements a distributed cognitive processor for allocation, reallocation, performance monitoring, and fabric morphing to optimize data transport and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If instantaneous analog-to-digital conversion is used to reduce latency, then data transport speed is improved, but processor and network load increases significantly

Engineering Contradiction:

ImprovelatencyVSAvoidprocessor and network load

Core Design Contradiction:

Loss of timeVSPower

Solution Approach 1:

The patent segments the processing load by introducing distributed processing nodes throughout the sensor network. Instead of centralized processing that overwhelms the network, sensor data is processed locally at distributed nodes, dividing the overall processing task into smaller manageable segments that reduce network traffic and processor burden while maintaining low latency through immediate local conversion and processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intelligent fabric and processing nodes as intermediaries between sensors and the central processor. These intermediary nodes perform analog-to-digital conversion and initial processing locally, acting as buffers that reduce the direct load on the central processor and network infrastructure while enabling fast data transport through optimized local processing paths.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple heterogeneous IP blocks are integrated to increase functionality, then system capability is improved, but interconnect complexity and wire delays increase

Engineering Contradiction:

Improvesystem capabilityVSAvoidinterconnect architecture

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent employs a reconfigurable intelligent fabric that dynamically adapts its interconnect architecture based on the specific requirements of integrated IP blocks. Rather than a fixed complex interconnect structure, the fabric can reconfigure routing paths, connection topologies, and resource allocation in real-time, enabling efficient integration of heterogeneous blocks while managing complexity through adaptive rather than static design.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The intelligent fabric utilizes parameter changes in the interconnect architecture, including variable routing paths, dynamic bandwidth allocation, and reconfigurable connection parameters. These parameter adjustments allow the system to optimize data flow between different IP blocks, reducing wire delays and managing interconnect complexity by adapting parameters rather than increasing structural complexity.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If distributed processing is implemented to reduce network load, then system efficiency is improved, but control and coordination complexity increases

Engineering Contradiction:

Improvesystem efficiencyVSAvoidcontrol complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal intelligent fabric that provides multiple functions within a single integrated structure. This fabric handles routing, switching, resource allocation, and coordination tasks simultaneously through a unified architecture, reducing control complexity compared to separate specialized systems while maintaining the benefits of distributed processing through its multi-functional capabilities.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The intelligent fabric incorporates feedback mechanisms that monitor system performance, resource utilization, and data flow patterns. This feedback enables automatic adjustment of routing decisions, resource allocation, and processing priorities, simplifying control coordination in distributed processing by using real-time information to optimize system operation without requiring complex centralized control logic.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS8103853B2Intelligent fabric system on a chip

Publication Date: 2012.01.24 THE BOEING CO

AI summary

A chip having an intelligent fabric may include a soft application processor, a reconfigurable hardware intelligent processor, a partitioned memory storage, and an interface to an external reconfigurable communication processor. The reconfigurable hardware intelligent processor may be configured to implement a distributed reconfigurable processor, and to provide cognitive control for at least one of allocation, reallocation, and performance monitoring.