Intelligent NIC Packet Parsing and Aggregation

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Solution Overview

Problem

Current packet aggregation methods in data transmission consume significant CPU resources due to the need for software parsing of packet headers to determine 5-tuple information and manage data flow, leading to inefficient CPU usage and increased bandwidth consumption.

Innovation Solution

An intelligent network interface card parses packet identifiers to determine data flow and sequence numbers, using direct memory access (DMA) to store packets in designated address spaces, thereby reducing the need for software copying and parsing, and maintaining aggregation information to facilitate efficient packet aggregation and processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If software parsing is used to extract 5-tuple information from packet headers, then data flow identification is achieved, but CPU resource consumption increases significantly

Engineering Contradiction:

Improvedata flow identification accuracyVSAvoidCPU resource consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces software-based packet parsing with hardware-based intelligent network interface card parsing. The NIC hardware directly extracts 5-tuple information and performs packet aggregation without requiring CPU intervention, thus resolving the contradiction between accurate data flow identification and high CPU consumption.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces an intermediary mechanism where the intelligent network interface card acts as a mediator between the physical network and the virtual machine. It pre-processes packets by extracting identifiers and managing aggregation information, reducing the processing burden on the CPU while maintaining accurate data flow identification.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If packets are aggregated through software copying, then packet aggregation is achieved, but processing efficiency decreases

Engineering Contradiction:

Improvepacket aggregation efficiencyVSAvoidprocessing efficiency

Core Design Contradiction:

ProductivityVSEase of operation

Solution Approach 1:

The patent replaces software-based packet copying with hardware-assisted direct memory access. The intelligent network interface card manages packet aggregation in hardware and uses DMA to transfer aggregated packets to the virtual machine's address space, eliminating the need for software copying operations and significantly improving processing efficiency.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent performs packet aggregation preliminarily in the intelligent network interface card before packets reach the virtual machine. By pre-aggregating packets and managing their address space allocation in advance, the system avoids inefficient software copying operations and improves overall processing efficiency.

Inventive Principle:

Principle #10Preliminary action

3Quantity of substance

If longer packets are used, then bandwidth utilization increases, but packet length must meet MTU requirements

Engineering Contradiction:

Improvebandwidth utilizationVSAvoidpacket length management complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces the intelligent network interface card as an intermediary that manages packet length transformation. It receives physical packets, extracts identifiers, and manages aggregation information to create virtual packets that can be longer than MTU limits while still meeting physical link requirements, thus improving bandwidth utilization without increasing complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces CPU resource consumption by eliminating the need for software parsing and copying, allowing for direct packet access and aggregation, thereby improving processing efficiency and bandwidth utilization.

Implementation Method 1

storing a payload of the first packet or storing a packet header and a payload of the first packet into the first address space through direct memory access (DMA)

Methodology Applied

Scientific EffectDirect Memory Access (DMA):

Data Source

PatentUS11616738B2Packet processing method and related device

Publication Date: 2023.03.28 HUAWEI TECH CO LTD

AI summary

A packet processing method and device are provided, to save CPU resources consumed by parsing a packet. The method includes: parsing, by an intelligent network interface card, a received first packet to obtain an identifier of the first packet; updating, by the intelligent network interface card, a control field of a first memory buffer based on the identifier of the first packet; storing, by the intelligent network interface card, a payload of the first packet or a packet header and a payload of the first packet into the first address space through DMA based on an aggregation position of the first packet; aggregating, by a host, the first address information and at least one piece of second address information based on an updated control field in the first mbuf; and reading, by a virtual machine, address information, to obtain data in an address space indicated by the address information.