Intelligent Throughput Router for Non-Volatile Memory
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Solution Overview
Problem
The write booster mode in memory systems temporarily improves write speeds but decreases the lifetime of the memory system due to increased write amplification, and is often used excessively or inadequately.
Innovation Solution
The memory system monitors parameters associated with write commands, such as the size of the write buffer and estimated throughput, to dynamically select between writing to high-density cell blocks or single-level cell blocks, thereby reducing write amplification and extending the memory system's lifetime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If write booster mode is activated to improve write speeds, then write performance is improved, but memory system lifetime is decreased due to increased write amplification
Solution Approach 1:
The system dynamically adjusts the write amplifier activation state based on real-time monitoring of write buffer utilization and command queue depth. The write amplifier transitions between active and inactive states according to throughput thresholds, making the system adaptive rather than static. This resolves the contradiction by enabling high-speed writes only when necessary (high buffer utilization) while conserving memory lifetime during low-demand periods.
Solution Approach 2:
The system changes the operational parameters of the write amplifier based on monitored conditions. When write buffer utilization exceeds a first threshold and command queue depth exceeds a second threshold, the write amplifier is activated to improve write speed. When these thresholds are not met, the write amplifier remains inactive to preserve memory lifetime, thus dynamically adjusting the parameter of write amplifier activation state.
2Productivity
If write amplifier is always active to maintain high write performance, then write speed is improved, but write amplification increases and reduces memory lifetime
Solution Approach 1:
The system implements feedback control by continuously monitoring write buffer utilization and command queue depth, then using this information to control write amplifier activation. The monitored parameters feed back to the control logic which adjusts write amplifier state accordingly. This feedback mechanism ensures the write amplifier operates only when throughput demands justify its activation, optimizing both productivity and energy efficiency.
Solution Approach 2:
The system employs periodic evaluation of throughput conditions to determine write amplifier activation. Rather than continuous operation, the write amplifier is activated in periodic bursts when throughput thresholds are exceeded, allowing the system to maintain high productivity during demand periods while reducing average write amplification and energy consumption over time.
3Productivity
If write buffer size is increased to handle higher throughput, then write performance is improved, but memory resource utilization is reduced
Solution Approach 1:
The system dynamically determines the effective write buffer size based on real-time throughput conditions. When throughput exceeds the first threshold, the system utilizes the full write buffer capacity to handle the load. When throughput is below the threshold, the system effectively uses a smaller buffer portion, preserving memory resources for other uses while still maintaining adequate buffering for normal operations.
Data Source
AI summary
Methods, systems, and devices for an intelligent throughput router are described. A memory system may monitor parameters associated with write commands being received. The memory system may select whether to write data to a first block type (e.g., a high density cell block) or a second block type (e.g., a single-level cell block) of a non-volatile memory device based on the parameters. The memory system may store data associated with write commands in a volatile storage area such as a write buffer, and monitor the size of the write buffer. The memory system may select the first block type or the second block type based on thresholds associated with usage of the write buffer. The memory system may estimate a throughput of data associated with the write commands, and select the first block type or the second block type based on thresholds associated with the throughput of data.