Intent-Based Timing Constraints for Digital IC Analysis
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Solution Overview
Problem
Traditional timing analysis methods for digital integrated circuits require explicit and repetitive assertion of timing constraints for each clock phase, leading to complexity, high runtime, and memory costs, as well as loss of intent in asserting constraints across different clock types.
Innovation Solution
The method involves defining intent groups for different clock types and associating timing constraints with these groups, allowing for intent-based assertions that cover all current and future clocks, eliminating the need for post-processing and reducing complexity by making assertions incremental and phase-independent.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If explicit and repetitive timing constraints are asserted for each clock phase, then timing analysis accuracy is maintained, but device complexity and runtime increase significantly
Solution Approach 1:
The patent creates intent groups that serve as universal containers for timing constraints applicable to multiple clock phases simultaneously. Instead of writing separate constraints for each phase, a single intent group can cover multiple phases, making the constraint system multi-functional and reducing repetition while maintaining coverage of all necessary timing relationships
Solution Approach 2:
The patent merges multiple individual timing constraints into consolidated intent groups. By combining constraints that apply to different clock phases into a single intent group structure, the system reduces the number of discrete constraint assertions needed while preserving the individual timing relationships through the group's internal phase associations
2Reliability
If explicit timing constraints are asserted for each clock phase, then complete timing coverage is achieved, but runtime and memory costs increase
Solution Approach 1:
The patent performs preliminary organization of timing constraints into intent groups before the actual timing analysis execution. By pre-structuring constraints into reusable groups that can be efficiently applied to multiple clock phases, the system reduces the computational overhead during runtime while ensuring complete timing coverage is maintained through the group's comprehensive phase associations
3Manufacturing precision
If explicit timing constraints are asserted for each clock phase, then precise timing control is achieved, but intent loss occurs across different clock types
Solution Approach 1:
The patent introduces intent groups as intermediary structures between the designer's intent and the detailed clock phase constraints. These groups act as mediators that preserve the high-level design intent while systematically applying it across multiple clock phases, preventing intent loss by maintaining a clear hierarchical relationship between the intent group and its associated phases
Data Source
AI summary
Timing analysis of a digital integrated circuit using intent based timing constraints includes defining a plurality of intent groups for an integrated circuit design. Each intent group is associated with a different clock type of the integrated circuit design. A different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design is associated with each intent group. One or more timing constraints is associated with each of the intent groups. A timing result is computed based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design.