Inter-block Scan Testing with Shared I/O Pads
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Solution Overview
Problem
Current scan test methods for integrated circuits (ICs) face challenges in efficiently testing inter-block circuits due to the need for a large number of input/output (I/O) components and complex control signals, which complicates the process of loading and unloading test patterns and results across different circuit blocks.
Innovation Solution
The integration of a control circuit with a de-multiplexer and clock control circuit allows for the separate loading and unloading of test patterns across multiple scan chains using shared I/O components, enabling efficient testing of inter-block circuits by generating selector signals to partition and combine test patterns and clock signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate I/O components are used for each circuit block to load and unload test patterns, then testing coverage is improved, but the number of I/O components increases and device complexity worsens
Solution Approach 1:
The shared I/O components are designed to serve multiple circuit blocks by dynamically switching their connection targets. The de-multiplexer and multiplexer enable a single I/O component to load test patterns into and unload test results from different scan chains belonging to different circuit blocks, thereby reducing the total number of I/O components while maintaining comprehensive testing coverage.
Solution Approach 2:
The test pattern is segmented into multiple portions, with each portion designated for a specific circuit block. The de-multiplexer separates the incoming test pattern bit stream into distinct portions and routes them to the appropriate scan chains. This segmentation approach allows shared I/O components to efficiently manage multiple circuit blocks without requiring dedicated I/O for each block.
2Ease of operation
If dedicated I/O components are allocated to each scan chain, then test pattern loading is simplified, but the quantity of I/O components increases
Solution Approach 1:
The de-multiplexer and multiplexer serve as intermediary components between the shared I/O and the multiple scan chains. These intermediaries manage the distribution and collection of test patterns and results, respectively, enabling a single I/O component to interact with multiple scan chains in a controlled manner. This intermediary approach maintains ease of operation while significantly reducing the quantity of I/O components required.
3Reliability
If multiple I/O components are used for testing inter-block circuits, then fault detection capability is improved, but manufacturing cost increases
Solution Approach 1:
The shared I/O components are configured to test inter-block circuits by sequentially or selectively connecting to different circuit blocks through the de-multiplexer and multiplexer. This multi-functional capability allows the same I/O infrastructure to detect faults across multiple blocks and inter-block connections, maintaining high fault detection capability while reducing the number of I/O components and associated manufacturing costs.
4Measurement precision
If separate loading and unloading operations are performed for each circuit block, then test accuracy is improved, but testing time increases
Solution Approach 1:
The system maintains continuous useful action by overlapping test operations across different circuit blocks. While one circuit block is being tested, the de-multiplexer can prepare test patterns for the next block, and the multiplexer can begin unloading results from previously tested blocks. This continuous operation reduces idle time and accelerates the overall testing process while maintaining test accuracy through proper sequencing and control.
Solution Approach 2:
The testing process employs periodic action by systematically cycling through different circuit blocks in a structured sequence. The de-multiplexer periodically switches between different scan chains to load test patterns, and the multiplexer periodically switches to unload results. This periodic cycling approach ensures that each circuit block receives adequate testing attention while optimizing the overall testing throughput and reducing total testing time.
Data Source
AI summary
An integrated circuit (IC) chip includes a first circuit block, a second circuit block, an inter-block circuit and a control circuit. The first circuit block is configured to form a first scan chain to set states of flip-flops in the first circuit block. The second circuit block is configured to form a second scan chain to set states of flip-flops in the second circuit block. The inter-block circuit interfaces the first circuit block and the second circuit block. The control circuit is configured to load a first portion and a second portion of a test pattern separately to the first scan chain and the second scan chain to set states of flip-flops in the first circuit block and the second circuit block, enable a test of the inter-block circuit to capture a test result, and unload the test result from the first scan chain and the second scan chain.