Inter-Chip Communication Circuit for Neural Network Training
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Solution Overview
Problem
The efficiency of inter-chip communication is limited by network latency and communication overheads, leading to suboptimal computation performance in multi-core processors during neural network training.
Innovation Solution
A circuit and method for inter-chip communication that includes scheduling, computation, and sending units, which process and transmit data efficiently by caching and storing processed data within the chip, reducing latency and improving communication efficiency through task scheduling and resource management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transmitted between chips through network communication, then inter-chip communication is enabled, but network latency reduces communication efficiency
Solution Approach 1:
The patent merges the communication function into the computation unit by integrating a sending unit directly within the computation unit. This allows data to be transmitted without leaving the chip, eliminating network latency while maintaining inter-chip communication capability through direct coupling between computation units on different chips.
2Productivity
If computation resources are allocated for data processing, then computation efficiency is improved, but communication overhead reduces overall performance
Solution Approach 1:
The patent enables continuous computation by allowing the computation unit to process new data while simultaneously transmitting previously processed data through the integrated sending unit. This overlapping of computation and communication operations eliminates idle time and maintains continuous productive action, reducing communication overhead impact on overall performance.
3Speed
If data is cached within the chip before transmission, then transmission speed is improved, but chip complexity increases
Solution Approach 1:
The patent makes the computation unit multi-functional by integrating both data processing and data transmission capabilities within the same unit. The sending unit, coupled to the computation unit, can directly transmit processed data without requiring separate caching structures, achieving fast transmission while avoiding the complexity increase that would result from dedicated cache memory for each function.
Data Source
AI summary
The present disclosure provides a circuit, method and system for inter-chip communication. The method is implemented in a computation apparatus, where the computation apparatus is included in a combined processing apparatus, and the combined processing apparatus includes a general interconnection interface and other processing apparatus. The computation apparatus interacts with other processing apparatus to jointly complete a computation operation specified by a user. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and other processing apparatus and is used for storing data of the computation apparatus and other processing apparatus.