Inter-chip Interconnect Interface for Multi-chip Memory Coherence
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Solution Overview
Problem
As the number of cores in multi-core networking chips increases to meet demand for processing power, managing access to on-chip and attached memory becomes more challenging, particularly due to constraints in memory access speed and implementing memory coherency across cores.
Innovation Solution
A new processor architecture is introduced, featuring an inter-chip interconnect interface that enables efficient cross-chip communications and memory coherence methods, allowing multiple chip devices to operate as a single system with shared resources and synchronized access to I/O devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cores in multi-core networking chips increases to meet demand for processing power, then processing speed is improved, but managing access to on-chip and attached memory becomes more challenging
Solution Approach 1:
The patent segments the memory system into on-chip memory and attached memory, with dedicated memory controllers for each. The interconnect interface is divided into multiple channels that can be independently managed, allowing each core to access memory through optimized paths and reducing the complexity of managing memory access across multiple cores.
2Productivity
If more cores are added to increase processing power, then computational capacity is improved, but implementing memory coherency across cores becomes more difficult
Solution Approach 1:
The patent introduces an inter-chip interconnect interface as an intermediary between multiple chip devices, which manages memory coherency protocols and synchronization. This intermediary handles the complex tasks of maintaining coherent memory states across cores in different chips, reducing the burden on individual cores while ensuring reliable memory coherency.
3Productivity
If multiple chip devices are used to scale computational capacity, then processing power is improved, but cross-chip communication efficiency decreases
Solution Approach 1:
The patent transitions from traditional serial cross-chip communication to a parallel multi-channel interconnect interface. By adding spatial dimensions through multiple simultaneous communication channels between chip devices, the system achieves higher aggregate bandwidth and reduced communication latency, effectively scaling computational capacity without sacrificing cross-chip communication efficiency.
Data Source
AI summary
A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received.