Dedicated Inter-Chip Interconnect for Multi-Chip Processing Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-chip processing systems, managing access to shared memory across multiple processor cores leads to increased communication latency and congestion due to the distances signals must traverse and the centralized interconnect controller architecture.
Innovation Solution
A multi-chip processing system architecture with dedicated inter-chip interconnect interfaces for each column of processor clusters, allowing direct communication between paired cache controllers on different chips, reducing latency and congestion by using column-specific paths and mirroring indices for efficient data routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a centralized interconnect controller architecture is used to manage access to shared memory across multiple processor cores, then memory access coordination is achieved, but communication latency and congestion increase due to the distances signals must traverse
Solution Approach 1:
The patent segments the monolithic interconnect controller into multiple distributed interconnect controllers, each associated with specific processor cores. This segmentation allows memory access coordination to be distributed across multiple controllers rather than centralized in one bottleneck, reducing communication latency while maintaining coordination reliability.
Solution Approach 2:
The patent introduces a new dimension to the interconnect architecture by adding vertical inter-chip communication paths alongside horizontal intra-chip paths. This multi-dimensional interconnect structure provides alternative routing paths, reducing congestion and latency by allowing signals to traverse through different spatial dimensions rather than being constrained to a single planar path.
2Adaptability or versatility
If multiple multi-core processor chips are interconnected via a centralized interconnect controller, then resource sharing and system coherence are achieved, but inter-chip communication delay increases due to signal traversal distance
Solution Approach 1:
The patent segments the inter-chip interconnect into multiple dedicated interfaces, each handling traffic for specific processor clusters. This segmentation creates multiple parallel communication channels between chips, allowing resource sharing while reducing inter-chip communication delay through concurrent transmissions and shorter signal paths.
Solution Approach 2:
The patent introduces interconnect interfaces as intermediary components between processor clusters and the inter-chip network. These intermediaries buffer, route, and manage communications between chips, enabling efficient resource sharing while minimizing communication delay through intelligent routing and local caching capabilities.
3Reliability
If communications between cache controllers reside in different chips via the interconnect controller, then system-wide cache coherence is maintained, but this path contributes to a major part of inter-chip communication traffic and congestion
Solution Approach 1:
The patent segments cache coherence management by assigning specific coherence responsibilities to distributed interconnect controllers and cache controllers on different chips. This segmentation allows coherence protocols to be executed locally where possible, reducing the need for long-distance communications and thereby reducing routing congestion while maintaining system-wide coherence.
Solution Approach 2:
The patent implements local quality by enabling cache controllers to manage coherence locally within their respective chips and clusters first, before escalating to inter-chip communications. This localized approach handles the majority of coherence traffic locally, reducing inter-chip traffic and routing congestion while maintaining overall system coherence through coordinated local actions.
Data Source
AI summary
Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.