Inter-chip Interconnect Width Variation for Dicing and Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to balance the impedance of inter-chip interconnects and the readiness in dicing of semiconductor wafers, as thinner interconnects improve dicing readiness but can elevate impedance, making power supply and signal transmission difficult.
Innovation Solution
The method involves forming inter-chip interconnects with narrower intermediate portions and wider connection end portions, allowing for improved dicing readiness while suppressing impedance elevation by adjusting the width of the interconnects and their positioning within the dicing region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thinner inter-chip interconnects are used to improve dicing readiness, then dicing readiness is improved, but impedance of the inter-chip interconnects increases
Solution Approach 1:
The inter-chip interconnect is designed with varying width along its length: narrower in the intermediate portion (to improve dicing readiness) and wider at the connection end portions (to maintain low impedance). This local variation in geometric properties resolves the contradiction by optimizing each section for its specific function.
Solution Approach 2:
The inter-chip interconnect is segmented into distinct portions with different widths: connection end portions connected to chip-composing portions and an intermediate portion between them. This segmentation allows different sections to serve different purposes - wide sections for electrical performance and narrow sections for dicing performance.
2Ease of manufacture
If the entire portion of inter-chip interconnect is narrowed to improve dicing readiness, then dicing readiness is improved, but impedance increases significantly
Solution Approach 1:
Instead of uniformly narrowing the entire interconnect, only the intermediate portion is narrowed while connection end portions remain wide. This localized quality change allows dicing readiness to be improved without significantly increasing impedance, as the wider connection portions maintain good electrical contact.
Solution Approach 2:
Rather than narrowing the entire interconnect (excessive action that would harm impedance), only the necessary intermediate portion is narrowed (partial action). This partial narrowing is sufficient to improve dicing readiness while minimizing the impact on impedance.
Data Source
AI summary
A semiconductor wafer having a plurality of interconnect layers, includes a plurality of chip-composing portions, a dicing region separating the chip-composing portions from each other, and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.