Inter-Chip Termination Control for High-Speed Data Bus Integrity
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Solution Overview
Problem
Semiconductor apparatuses face signal distortion due to external noise and impedance mismatch, which existing on-die termination circuits struggle to address effectively, especially as operation speed increases and power consumption decreases.
Innovation Solution
A semiconductor apparatus comprising first and second chips, where each chip includes termination control circuits that generate and transmit termination control signals to set termination resistance values on the data bus, enabling Non-Target On-Die Termination by adjusting impedance to match transmission and reception ends, thereby reducing noise and reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operation speed of semiconductor apparatus is increased, then productivity is improved, but signal distortion occurs due to external noise and impedance mismatch
Solution Approach 1:
The patent implements dynamic termination control where the termination resistance is adjusted based on the operational state of the semiconductor apparatus. The termination control circuit receives control signals that indicate whether the apparatus is in a high-speed or low-speed mode, and accordingly adjusts the termination resistance value to match the impedance requirements for the current operating condition, thereby maintaining signal quality across different speeds
Solution Approach 2:
The patent changes the termination resistance parameter according to the operating speed. By providing different termination resistance values for high-speed and low-speed operations, the system optimizes signal transmission for each mode. The termination control circuit selectively applies appropriate resistance values based on the operational state, resolving the impedance mismatch problem that arises at higher speeds
2Use of energy by moving object
If power consumption of semiconductor apparatus is decreased, then use of energy is improved, but signal transmission becomes more susceptible to external noise
Solution Approach 1:
The termination control circuit dynamically adjusts termination resistance based on power consumption levels and operational mode. When the semiconductor apparatus operates in a low-power mode, the circuit modifies the termination resistance to compensate for increased noise susceptibility, thereby maintaining signal integrity without requiring higher power consumption
Solution Approach 2:
The patent modifies the termination resistance parameter in response to power consumption changes. By providing different termination configurations for high-power and low-power operational states, the system ensures that signal transmission remains robust against external noise even when operating at reduced power levels
3Reliability
If impedance mismatch occurs between transmitting and receiving ends, then signal distortion increases, but adding termination circuits increases device complexity
Solution Approach 1:
The termination control circuit is designed to perform multiple functions: it monitors the operational state of the semiconductor apparatus, determines the appropriate termination resistance value, and adjusts the termination accordingly. This multi-functional approach eliminates the need for separate termination circuits for different operating modes, reducing overall device complexity while maintaining signal transmission quality
Solution Approach 2:
The patent merges the termination control functionality with the existing operational control circuitry of the semiconductor apparatus. By integrating the termination control circuit into the existing control structure and using the same control signals for both operational mode determination and termination adjustment, the system reduces device complexity while effectively addressing impedance mismatch
Data Source
AI summary
A semiconductor apparatus includes a first chip and a second chip. The first chip provides a first termination control signal to the second chip and the second chip provides a termination resistance for the first chip based on the first termination control signal, when the first chip receives data.