Inter-chip Time Synchronization for Wireless Audio Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In distributed wireless systems, the synchronization of audio signals across multiple devices is hindered by latency and clock discrepancies between host processors and network interfaces, leading to noticeable artifacts in audio rendering.
Innovation Solution
An inter-chip time synchronization system that determines conversion parameters to align timestamps captured by network interface clocks with host processor clocks, enabling precise synchronization for operations like audio beamforming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wireless transmission is used to convey audio signals between devices, then wireless connectivity and flexibility are achieved, but latency is introduced causing audio information to not be rendered simultaneously
Solution Approach 1:
The system performs preliminary actions by capturing timestamps at the network interface before wireless transmission occurs, and by pre-calculating conversion parameters between clock domains. This allows the system to compensate for transmission latency through timestamp conversion rather than requiring real-time synchronization during audio rendering.
2Measurement precision
If timestamps are captured using network interface clock instead of host processor clock, then timing resolution is improved, but clock domain discrepancies introduce synchronization errors
Solution Approach 1:
The patent introduces an intermediary mechanism - the timestamp conversion process - that bridges the network interface clock domain and host processor clock domain. Conversion parameters are calculated to translate timestamps from the high-resolution network interface clock to the host processor clock domain, allowing the system to preserve timing precision while eliminating synchronization errors between clock domains.
3Loss of time
If wired connection is used to convey audio signals, then simultaneous arrival at speakers is achieved, but device mobility and wireless flexibility are lost
Solution Approach 1:
The system creates a temporal copy of the transmission timing information through timestamp capture. By recording when packets were transmitted or received and then converting these timestamps to account for wireless latency, the system replicates the simultaneity achievement of wired connections without requiring physical wire connections, thus maintaining wireless flexibility.
Data Source
AI summary
A device implementing an inter-chip time synchronization system may include a first circuit having a first clock and a second circuit having a second clock. The first circuit may be configured to capture a first timestamp from the first clock responsive to receiving a sampling signal from the second circuit. The first circuit may be configured to receive a second timestamp that was captured by the second circuit from a second clock of the second circuit. The second timestamp may have been captured by the second circuit when the sampling signal was transmitted to the first circuit. The first circuit may be configured to generate a conversion parameter for converting from the second clock of the second circuit to the first clock of the first circuit based at least in part on the first and second timestamps, and to store the generated conversion parameter.