Multi-core Inter-core Communication via Shared Memory DMA
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Solution Overview
Problem
In multi-core processing systems, inter-core communication faces challenges with large access delays due to complex data transmission requirements across integrated Central Processing Units (CPUs) in a System On Chip (SOC).
Innovation Solution
The proposed solution involves an inter-core communication method using a shared memory and Direct Memory Access (DMA) for a multi-core processing system. This method includes reading and parsing messages in the shared memory to determine source and destination addresses, allocating storage space based on data length, and using DMA to transfer data between storage spaces corresponding to these addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data transmission is performed through traditional inter-core communication methods in multi-core processing systems, then data can be transmitted between cores, but large access delays occur due to complex transmission requirements
Solution Approach 1:
The patent introduces a shared memory as an intermediary between transmitting and receiving cores. The transmitting core writes data to the shared memory, and the receiving core reads from it, eliminating the need for complex direct inter-core communication protocols. This mediator approach simplifies the communication path and reduces access delays.
Solution Approach 2:
The patent replaces traditional CPU-based data transmission mechanisms with Direct Memory Access (DMA). Instead of using CPU instructions to move data between cores (mechanical system), the DMA controller automatically handles data transfer in the background, substituting the complex CPU-mediated transmission with a more efficient memory-access-based approach.
2Productivity
If CPU is used for data transmission tasks in inter-core communication, then data can be transmitted, but CPU efficiency decreases due to involvement in transmission overhead
Solution Approach 1:
The patent extracts the data transmission function from the CPU by introducing a DMA controller. The CPU is taken out of the data transmission loop and focuses only on high-level processing tasks, while the DMA controller handles the actual data movement between shared memory and destination. This separation improves CPU efficiency by eliminating transmission overhead from CPU operations.
Solution Approach 2:
The DMA controller implements self-service by automatically managing data transmission without CPU intervention. Once the CPU initiates a DMA transfer by setting up the transfer parameters, the DMA controller autonomously handles the entire data movement process, including memory access and data routing, thereby freeing the CPU for other productive tasks.
3Adaptability or versatility
If fixed storage space allocation is used for inter-core communication, then memory management is simplified, but flexibility in data storage is reduced
Solution Approach 1:
The patent implements dynamic storage space allocation in the shared memory for inter-core communication. Instead of fixed-size buffers, the system allocates memory space based on the actual data size being transmitted. The shared memory can adaptively adjust the allocation size for each communication event, providing flexibility for varying data lengths while maintaining efficient memory utilization through dynamic rather than static allocation.
Data Source
AI summary
Provided are a multi-core processing system and an inter-core communication method therefor, and a storage medium. The method includes: reading from a shared memory a message written by a transmitting core, and parsing the message to obtain a source address of and a data length of data to be transmitted (S102); performing storage space allocation based on the data length to obtain a destination address of the data to be transmitted (S104); and transmitting the data to be transmitted from a storage space corresponding to the source address to a storage space corresponding to the destination address by means of Direct Memory Access (DMA), based on the source address, the data length, and the destination address (S106).