Inter-Core Interference Detection in Memory Controllers
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Solution Overview
Problem
Current memory controller systems fail to effectively reduce inter-core interference in multi-core processors, as they do not accurately track and account for lower-level memory request behaviors, leading to poor memory scheduling decisions, reduced performance, and increased power consumption.
Innovation Solution
Implementing an intercore interference monitor that tracks interference events such as bank contention, row-buffer conflicts, and bus contention using counters, and generates control signals to optimize scheduling decisions and reduce interference across cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-level metrics such as memory request rate are used for scheduling decisions, then bandwidth utilization is improved, but inter-core interference cannot be effectively detected or reduced
Solution Approach 1:
The patent segments the monitoring granularity from high-level core-level metrics to low-level bank-level and row-buffer-level metrics. The interference monitor divides memory access patterns into discrete interference events at the bank and row-buffer level, enabling precise identification of interference sources while maintaining overall system productivity.
Solution Approach 2:
The patent adds a new dimension of monitoring by tracking inter-core interference events as a separate metric dimension alongside traditional bandwidth metrics. The interference monitor operates in parallel with the memory scheduler, adding an orthogonal layer of observation that captures interference without disrupting the primary bandwidth management function.
2Ease of operation
If memory resources are distributed evenly based on bandwidth capacity, then fairness is improved, but actual core needs and interference impact are not accounted for
Solution Approach 1:
The patent implements feedback by having the interference monitor continuously track interference events and feed this information back to the memory scheduler. The scheduler uses this feedback to dynamically adjust scheduling decisions, moving from static even distribution to adaptive allocation that responds to actual interference conditions and core needs.
Solution Approach 2:
The patent transforms the static resource distribution approach into a dynamic one where scheduling priorities can change based on real-time interference measurements. The system adapts scheduling behavior dynamically by adjusting priorities for cores experiencing high interference versus those with low interference, making the system versatile to different operational conditions.
3Productivity
If existing interference reduction solutions are implemented, then bandwidth fairness is improved, but direct interaction between cores and lower-level interference patterns are not tracked
Solution Approach 1:
The patent applies preliminary action by having the interference monitor track and attribute interference events before they significantly impact system performance. By continuously monitoring bank and row-buffer level events in advance, the system can identify emerging interference patterns and take preventive scheduling actions before performance degradation occurs.
Solution Approach 2:
The patent introduces an intermediary component - the interference monitor - that sits between the memory scheduler and the physical memory banks. This intermediary translates low-level bank and row-buffer events into high-level interference metrics that the scheduler can understand and act upon, making lower-level tracking feasible without overwhelming complexity.
4Device complexity
If memory controllers do not track interference caused by various cores, then device complexity is reduced, but memory scheduling decisions become suboptimal leading to reduced performance and increased power consumption
Solution Approach 1:
The patent implements self-service by having the memory controller's own interference monitor provide scheduling information to the memory scheduler. The interference monitoring and scheduling functions are integrated within the same controller, eliminating the need for external complex tracking infrastructure while achieving optimal scheduling decisions through locally available interference data.
Data Source
AI summary
Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus contentions, row-buffer conflicts, and increased write-to-read turnaround time caused by a first core in the processor-based system that causes a delay in access to the memory by a second core in the processor-based system; deriving a control signal based on the number of interference events; and transmitting the control signal to one or more resources of the processor-based system to reduce the number of interference events from an original number of interference events.