Inter-core Communication via Postbox and Bus Adapter
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Solution Overview
Problem
Existing multi-core processor communication technologies face challenges with high complexity, poor timeliness, and limited expandability, particularly due to reliance on shared memory and complex software interactions, which reduce efficiency and increase resource consumption.
Innovation Solution
A device comprising a postbox component for message storage and notification, and a bus adapter component providing read/write interfaces between cores, along with an arbiter for arbitration, simplifies communication by reducing software interactions and using a distributed structure to manage mutual exclusion and interrupt requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If shared memory is used for inter-core communication, then message passing can be implemented, but communication complexity increases due to spin lock resources and synchronous operations
Solution Approach 1:
The communication mechanism is segmented into dedicated message queues for each core pair, separating communication traffic from general data traffic. Each message queue operates independently with its own head and tail pointers, eliminating the need for spin locks and synchronous operations that plague shared memory approaches.
Solution Approach 2:
A message queue structure acts as an intermediary between sending and receiving cores, providing buffered asynchronous communication. The queue absorbs timing differences between cores, eliminating the need for spin lock resources and complex synchronous operations required by direct shared memory access.
2Ease of operation
If shared memory is used for inter-core communication, then message passing can be achieved, but communication timeliness deteriorates due to software interaction steps
Solution Approach 1:
The message queue operates autonomously without requiring operating system software intervention. The sending core writes messages to the queue and the receiving core reads from it directly, with hardware-managed head/tail pointers automatically tracking message positions. This eliminates multiple software interaction steps including lock acquisition, context switching, and interrupt handling that cause time delays in shared memory approaches.
Solution Approach 2:
Message queues are pre-configured with head and tail pointers during system initialization, establishing the communication path before actual message passing begins. This preliminary setup eliminates runtime configuration overhead and software interaction steps that would otherwise increase communication latency.
3Productivity
If the number of cores is increased, then parallel computing capability is improved, but communication reliability deteriorates due to increased complexity
Solution Approach 1:
The communication system is segmented into dedicated message queues for each core pair, creating isolated communication channels. This segmentation prevents communication errors from propagating across multiple cores and simplifies debugging and verification as each queue can be independently validated.
Solution Approach 2:
The message queue structure provides a universal communication interface that works consistently across all core combinations. The same queue-based mechanism handles communication between any pair of cores, providing reliable and consistent behavior regardless of the number of cores in the system.
4Use of energy by moving object
If shared memory bandwidth is shared with data traffic, then resource utilization is improved, but communication timeliness becomes uncertain
Solution Approach 1:
The bus interface is segmented into separate message queue interfaces that provide dedicated communication paths. Message traffic and data traffic use different interface paths, ensuring that message communication timeliness is not affected by data traffic load while still allowing full utilization of available bandwidth resources.
Data Source
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AI summary
A device and method for communicating between cores are provided. The device comprises: a postbox component, configured to store a message sent from a message sending core to a message receiving core and notify the message receiving core to read the message; and a bus adapter component, connected between the postbox component and the message receiving core and the message sending core which communicate with each other and configured to provide read/write interfaces of the postbox component and the message receiving core and the message sending core. By means of the present invention, the problems that the device and method for communicating between cores with high complexity, poor timeliness and poor expandability during multi-core application in the related art are solved, thereby achieving the effects of reducing the communication between cores complexity significantly, reducing communication time delay and having excellent expandability and scalability.